perf/x86/intel/uncore: Add Sapphire Rapids server PCU support

mainline inclusion
from mainline-v5.15-rc1
commit 0654dfdc
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO



Intel-SIG: commit 0654dfdc perf/x86/intel/uncore: Add Sapphire
Rapids server PCU support
This commit is backported for SPR PMU uncore support.

-------------------------------------

The PCU is the primary power controller for the Sapphire Rapids.

Except the name, all the information can be retrieved from the discovery
tables.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-7-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>