Commit 719fce75 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC fixes from Arnd Bergmann:
 "The code changes address mostly minor problems:

   - Several NXP/FSL SoC driver fixes, addressing issues with error
     handling and compilation

   - Fix a clock disabling imbalance in gpcv2 driver.

   - Arm Juno DMA coherency issue

   - Trivial firmware driver fixes for op-tee and scmi firmware

  The remaining changes address issues in the devicetree files:

   - A timer regression for the OMAP devkit8000, which has to use the
     alternative timer.

   - A hang in the i.MX8MM power domain configuration

   - Multiple fixes for the Rockchip RK3399 addressing issues with sound
     and eMMC

   - Cosmetic fixes for i.MX8ULP, RK3xxx, and Tegra124"

* tag 'soc-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits)
  ARM: tegra: Move panels to AUX bus
  soc: imx: gpcv2: Fix clock disabling imbalance in error path
  soc: fsl: qe: Check of ioremap return value
  soc: fsl: qe: fix typo in a comment
  soc: fsl: guts: Add a missing memory allocation failure check
  soc: fsl: guts: Revert commit 3c0d64e8
  soc: fsl: Correct MAINTAINERS database (SOC)
  soc: fsl: Correct MAINTAINERS database (QUICC ENGINE LIBRARY)
  soc: fsl: Replace kernel.h with the necessary inclusions
  dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
  dt-bindings: qoriq-clock: add missing compatible for lx2160a
  ARM: dts: Use 32KiHz oscillator on devkit8000
  ARM: dts: switch timer config to common devkit8000 devicetree
  tee: optee: fix error return code in probe function
  arm64: dts: imx8ulp: Set #thermal-sensor-cells to 1 as required
  arm64: dts: imx8mm: Fix VPU Hanging
  ARM: dts: rockchip: fix a typo on rk3288 crypto-controller
  ARM: dts: rockchip: reorder rk322x hmdi clocks
  firmware: arm_scmi: Remove space in MODULE_ALIAS name
  arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
  ...
parents 201b5c01 c253bf70
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+6 −0
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@@ -895,6 +895,12 @@ S: 3000 FORE Drive
S: Warrendale, Pennsylvania 15086
S: Warrendale, Pennsylvania 15086
S: USA
S: USA


N: Ludovic Desroches
E: ludovic.desroches@microchip.com
D: Maintainer for ARM/Microchip (AT91) SoC support
D: Author of ADC, pinctrl, XDMA and SDHCI drivers for this platform
S: France

N: Martin Devera
N: Martin Devera
E: devik@cdi.cz
E: devik@cdi.cz
W: http://luxik.cdi.cz/~devik/qos/
W: http://luxik.cdi.cz/~devik/qos/
+2 −1
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@@ -8,7 +8,8 @@ title: Atmel AT91 device tree bindings.


maintainers:
maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - Alexandre Belloni <alexandre.belloni@bootlin.com>
  - Ludovic Desroches <ludovic.desroches@microchip.com>
  - Claudiu Beznea <claudiu.beznea@microchip.com>
  - Nicolas Ferre <nicolas.ferre@microchip.com>


description: |
description: |
  Boards with a SoC of the Atmel AT91 or SMART family shall have the following
  Boards with a SoC of the Atmel AT91 or SMART family shall have the following
+1 −1
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@@ -8,7 +8,7 @@ Required properties:
  - compatible: Should contain a chip-specific compatible string,
  - compatible: Should contain a chip-specific compatible string,
	Chip-specific strings are of the form "fsl,<chip>-dcfg",
	Chip-specific strings are of the form "fsl,<chip>-dcfg",
	The following <chip>s are known to be supported:
	The following <chip>s are known to be supported:
	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a


  - reg : should contain base address and length of DCFG memory-mapped registers
  - reg : should contain base address and length of DCFG memory-mapped registers


+1 −0
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@@ -44,6 +44,7 @@ Required properties:
	* "fsl,ls1046a-clockgen"
	* "fsl,ls1046a-clockgen"
	* "fsl,ls1088a-clockgen"
	* "fsl,ls1088a-clockgen"
	* "fsl,ls2080a-clockgen"
	* "fsl,ls2080a-clockgen"
	* "fsl,lx2160a-clockgen"
	Chassis-version clock strings include:
	Chassis-version clock strings include:
	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
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@@ -53,6 +53,7 @@ properties:
          - const: st,stm32mp15-hsotg
          - const: st,stm32mp15-hsotg
          - const: snps,dwc2
          - const: snps,dwc2
      - const: samsung,s3c6400-hsotg
      - const: samsung,s3c6400-hsotg
      - const: intel,socfpga-agilex-hsotg


  reg:
  reg:
    maxItems: 1
    maxItems: 1
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