Unverified Commit c253bf70 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'soc-fsl-fix-v5.17' of... 

Merge tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/fixes

NXP/FSL SoC driver fixes for v5.17

- Add missing SoC compatible in existing binding
- Replace kernel.h with the necessary inclusions
- MAINTAINERS file fixes
- Fix memory allocation failure check in guts driver
- Various cleanups and minor fixes

* tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
  soc: fsl: qe: Check of ioremap return value
  soc: fsl: qe: fix typo in a comment
  soc: fsl: guts: Add a missing memory allocation failure check
  soc: fsl: guts: Revert commit 3c0d64e8
  soc: fsl: Correct MAINTAINERS database (SOC)
  soc: fsl: Correct MAINTAINERS database (QUICC ENGINE LIBRARY)
  soc: fsl: Replace kernel.h with the necessary inclusions
  dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
  dt-bindings: qoriq-clock: add missing compatible for lx2160a

Link: https://lore.kernel.org/r/20220219012208.21835-1-leoyang.li@nxp.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f03f10a9 a222fd85

Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ Required properties: 
  - compatible: Should contain a chip-specific compatible string,

	Chip-specific strings are of the form "fsl,<chip>-dcfg",

	The following <chip>s are known to be supported:

	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.

	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a



  - reg : should contain base address and length of DCFG memory-mapped registers

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ Required properties: 
	* "fsl,ls1046a-clockgen"

	* "fsl,ls1088a-clockgen"

	* "fsl,ls2080a-clockgen"

	* "fsl,lx2160a-clockgen"

	Chassis-version clock strings include:

	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks

	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -7750,8 +7750,7 @@ M: Qiang Zhao <qiang.zhao@nxp.com> 
L:	linuxppc-dev@lists.ozlabs.org

S:	Maintained

F:	drivers/soc/fsl/qe/

F:	include/soc/fsl/*qe*.h

F:	include/soc/fsl/*ucc*.h

F:	include/soc/fsl/qe/









FREESCALE QUICC ENGINE UCC ETHERNET DRIVER









M:	Li Yang <leoyang.li@nxp.com>








@@ -7782,6 +7781,7 @@ F:	Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml







F:	Documentation/devicetree/bindings/soc/fsl/









F:	drivers/soc/fsl/









F:	include/linux/fsl/









F:	include/soc/fsl/

















FREESCALE SOC FS_ENET DRIVER









M:	Pantelis Antoniou <pantelis.antoniou@gmail.com>
































drivers/soc/fsl/guts.c



+9
−5






























Original line number
Diff line number
Diff line







@@ -28,7 +28,6 @@ struct fsl_soc_die_attr {







static struct guts *guts;









static struct soc_device_attribute soc_dev_attr;









static struct soc_device *soc_dev;









static struct device_node *root;





























/* SoC die attribute definition for QorIQ platform */








@@ -138,7 +137,7 @@ static u32 fsl_guts_get_svr(void)

















static int fsl_guts_probe(struct platform_device *pdev)









{









	struct device_node *np = pdev->dev.of_node;









	struct device_node *root, *np = pdev->dev.of_node;









	struct device *dev = &pdev->dev;









	const struct fsl_soc_die_attr *soc_die;









	const char *machine;








@@ -159,8 +158,14 @@ static int fsl_guts_probe(struct platform_device *pdev)







	root = of_find_node_by_path("/");









	if (of_property_read_string(root, "model", &machine))









		of_property_read_string_index(root, "compatible", 0, &machine);









	if (machine)









		soc_dev_attr.machine = machine;









	if (machine) {









		soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);









		if (!soc_dev_attr.machine) {









			of_node_put(root);









			return -ENOMEM;









		}









	}









	of_node_put(root);



















	svr = fsl_guts_get_svr();









	soc_die = fsl_soc_die_match(svr, fsl_soc_die);








@@ -195,7 +200,6 @@ static int fsl_guts_probe(struct platform_device *pdev)







static int fsl_guts_remove(struct platform_device *dev)









{









	soc_device_unregister(soc_dev);









	of_node_put(root);









	return 0;









}










































drivers/soc/fsl/qe/qe.c



+2
−2






























Original line number
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Diff line







@@ -147,7 +147,7 @@ EXPORT_SYMBOL(qe_issue_cmd);







 * memory mapped space.









 * The BRG clock is the QE clock divided by 2.









 * It was set up long ago during the initial boot phase and is









 * is given to us.









 * given to us.









 * Baud rate clocks are zero-based in the driver code (as that maps









 * to port numbers). Documentation uses 1-based numbering.









 */