Unverified Commit 7133713a authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!14627 crypto: hisilicon/qm - inject error before stopping queue 

Merge Pull Request from: @ci-robot 
 
PR sync from: Guo Mengqi <guomengqi3@huawei.com>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/YIFIT5XKADVRW5CM5ANK6VRJNAYGTQUZ/ 
 
https://gitee.com/src-openeuler/kernel/issues/IAYQSI 
 
Link:https://gitee.com/openeuler/kernel/pulls/14627

 

Reviewed-by: default avatarLi Nan <linan122@huawei.com>
Signed-off-by: default avatarLi Nan <linan122@huawei.com>
parents 17c9d5ef 8ace7c25

drivers/crypto/hisilicon/qm.c

+24 −24
Original line number Diff line number Diff line
@@ -4196,6 +4196,28 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set) 
	return -ETIMEDOUT;

}



static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)

{

	u32 nfe_enb = 0;



	/* Kunpeng930 hardware automatically close master ooo when NFE occurs */

	if (qm->ver >= QM_HW_V3)

		return;



	if (!qm->err_status.is_dev_ecc_mbit &&

	    qm->err_status.is_qm_ecc_mbit &&

	    qm->err_ini->close_axi_master_ooo) {

		qm->err_ini->close_axi_master_ooo(qm);

	} else if (qm->err_status.is_dev_ecc_mbit &&

		   !qm->err_status.is_qm_ecc_mbit &&

		   !qm->err_ini->close_axi_master_ooo) {

		nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);

		writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,

		       qm->io_base + QM_RAS_NFE_ENABLE);

		writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);

	}

}



static int qm_vf_reset_prepare(struct hisi_qm *qm,

			       enum qm_stop_reason stop_reason)

{
@@ -4260,6 +4282,8 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm) 
		return ret;

	}



	qm_dev_ecc_mbit_handle(qm);



	/* PF obtains the information of VF by querying the register. */

	qm_cmd_uninit(qm);
@@ -4288,28 +4312,6 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm) 
	return 0;

}



static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)

{

	u32 nfe_enb = 0;



	/* Kunpeng930 hardware automatically close master ooo when NFE occurs */

	if (qm->ver >= QM_HW_V3)

		return;



	if (!qm->err_status.is_dev_ecc_mbit &&

	    qm->err_status.is_qm_ecc_mbit &&

	    qm->err_ini->close_axi_master_ooo) {

		qm->err_ini->close_axi_master_ooo(qm);

	} else if (qm->err_status.is_dev_ecc_mbit &&

		   !qm->err_status.is_qm_ecc_mbit &&

		   !qm->err_ini->close_axi_master_ooo) {

		nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);

		writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,

		       qm->io_base + QM_RAS_NFE_ENABLE);

		writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);

	}

}



static int qm_soft_reset_prepare(struct hisi_qm *qm)

{

	struct pci_dev *pdev = qm->pdev;
@@ -4335,8 +4337,6 @@ static int qm_soft_reset_prepare(struct hisi_qm *qm) 
		return ret;

	}



	qm_dev_ecc_mbit_handle(qm);



	/* OOO register set and check */

	writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,

	       qm->io_base + ACC_MASTER_GLOBAL_CTRL);