Commit 8ace7c25 authored by Weili Qian's avatar Weili Qian Committed by Guo Mengqi
Browse files

crypto: hisilicon/qm - inject error before stopping queue 

stable inclusion
from stable-v6.1.113
commit 98d3be34c9153eceadb56de50d9f9347e88d86e4
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/IAYQSI
CVE: CVE-2024-47730

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=98d3be34c9153eceadb56de50d9f9347e88d86e4



--------------------------------

[ Upstream commit b04f06fc0243600665b3b50253869533b7938468 ]

The master ooo cannot be completely closed when the
accelerator core reports memory error. Therefore, the driver
needs to inject the qm error to close the master ooo. Currently,
the qm error is injected after stopping queue, memory may be
released immediately after stopping queue, causing the device to
access the released memory. Therefore, error is injected to close master
ooo before stopping queue to ensure that the device does not access
the released memory.

Fixes: 6c6dd580 ("crypto: hisilicon/qm - add controller reset interface")
Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Conflicts:
	drivers/crypto/hisilicon/qm.c
[context conflict]
Signed-off-by: default avatarGuo Mengqi <guomengqi3@huawei.com>
parent d51fb86c

drivers/crypto/hisilicon/qm.c

+24 −24
Original line number Diff line number Diff line
@@ -4196,6 +4196,28 @@ static int qm_set_vf_mse(struct hisi_qm *qm, bool set) 
	return -ETIMEDOUT;

}



static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)

{

	u32 nfe_enb = 0;



	/* Kunpeng930 hardware automatically close master ooo when NFE occurs */

	if (qm->ver >= QM_HW_V3)

		return;



	if (!qm->err_status.is_dev_ecc_mbit &&

	    qm->err_status.is_qm_ecc_mbit &&

	    qm->err_ini->close_axi_master_ooo) {

		qm->err_ini->close_axi_master_ooo(qm);

	} else if (qm->err_status.is_dev_ecc_mbit &&

		   !qm->err_status.is_qm_ecc_mbit &&

		   !qm->err_ini->close_axi_master_ooo) {

		nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);

		writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,

		       qm->io_base + QM_RAS_NFE_ENABLE);

		writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);

	}

}



static int qm_vf_reset_prepare(struct hisi_qm *qm,

			       enum qm_stop_reason stop_reason)

{
@@ -4260,6 +4282,8 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm) 
		return ret;

	}



	qm_dev_ecc_mbit_handle(qm);



	/* PF obtains the information of VF by querying the register. */

	qm_cmd_uninit(qm);
@@ -4288,28 +4312,6 @@ static int qm_controller_reset_prepare(struct hisi_qm *qm) 
	return 0;

}



static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)

{

	u32 nfe_enb = 0;



	/* Kunpeng930 hardware automatically close master ooo when NFE occurs */

	if (qm->ver >= QM_HW_V3)

		return;



	if (!qm->err_status.is_dev_ecc_mbit &&

	    qm->err_status.is_qm_ecc_mbit &&

	    qm->err_ini->close_axi_master_ooo) {

		qm->err_ini->close_axi_master_ooo(qm);

	} else if (qm->err_status.is_dev_ecc_mbit &&

		   !qm->err_status.is_qm_ecc_mbit &&

		   !qm->err_ini->close_axi_master_ooo) {

		nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);

		writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,

		       qm->io_base + QM_RAS_NFE_ENABLE);

		writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);

	}

}



static int qm_soft_reset_prepare(struct hisi_qm *qm)

{

	struct pci_dev *pdev = qm->pdev;
@@ -4335,8 +4337,6 @@ static int qm_soft_reset_prepare(struct hisi_qm *qm) 
		return ret;

	}



	qm_dev_ecc_mbit_handle(qm);



	/* OOO register set and check */

	writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,

	       qm->io_base + ACC_MASTER_GLOBAL_CTRL);