Commit 7110569a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk-next 

 - Migrate some clk drivers to clk_divider_ops.determine_rate

* clk-renesas:
  clk: renesas: Make CLK_R9A06G032 invisible
  clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
  dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
  clk: renesas: r9a07g044: Add clock and reset entries for ADC
  clk: renesas: r9a07g044: Add clock and reset entries for CANFD
  clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
  clk: renesas: r9a07g044: Add GPIO clock and reset entries
  clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
  clk: renesas: r9a07g044: Add USB clocks/resets
  clk: renesas: r9a07g044: Add DMAC clocks/resets
  clk: renesas: r9a07g044: Add I2C clocks/resets
  clk: renesas: r8a779a0: Add the DSI clocks
  clk: renesas: r8a779a0: Add the DU clock
  clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic
  clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
  clk: renesas: rzg2l: Avoid mixing error pointers and NULL
  clk: renesas: rzg2l: Fix a double free on error
  clk: renesas: rzg2l: Fix return value and unused assignment
  clk: renesas: rzg2l: Remove unneeded semicolon

* clk-cleanup:
  clk: palmas: Add a missing SPDX license header
  clk: Align provider-specific CLK_* bit definitions

* clk-determine-divider:
  clk: stm32mp1: Switch to clk_divider.determine_rate
  clk: stm32h7: Switch to clk_divider.determine_rate
  clk: stm32f4: Switch to clk_divider.determine_rate
  clk: bcm2835: Switch to clk_divider.determine_rate
  clk: divider: Implement and wire up .determine_rate by default
parents 4990d8c1 a1cde1f0 28fc39f7 23a57ee7

drivers/clk/bcm/clk-bcm2835.c

+4 −5
Original line number Diff line number Diff line
@@ -805,11 +805,10 @@ static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 
	return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);

}



static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,

					   unsigned long rate,

					   unsigned long *parent_rate)

static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,

					      struct clk_rate_request *req)

{

	return clk_divider_ops.round_rate(hw, rate, parent_rate);

	return clk_divider_ops.determine_rate(hw, req);

}



static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
@@ -901,7 +900,7 @@ static const struct clk_ops bcm2835_pll_divider_clk_ops = { 
	.unprepare = bcm2835_pll_divider_off,

	.recalc_rate = bcm2835_pll_divider_get_rate,

	.set_rate = bcm2835_pll_divider_set_rate,

	.round_rate = bcm2835_pll_divider_round_rate,

	.determine_rate = bcm2835_pll_divider_determine_rate,

	.debug_init = bcm2835_pll_divider_debug_init,

};

drivers/clk/clk-divider.c

+23 −0
Original line number Diff line number Diff line
@@ -446,6 +446,27 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, 
				  divider->width, divider->flags);

}



static int clk_divider_determine_rate(struct clk_hw *hw,

				      struct clk_rate_request *req)

{

	struct clk_divider *divider = to_clk_divider(hw);



	/* if read only, just return current value */

	if (divider->flags & CLK_DIVIDER_READ_ONLY) {

		u32 val;



		val = clk_div_readl(divider) >> divider->shift;

		val &= clk_div_mask(divider->width);



		return divider_ro_determine_rate(hw, req, divider->table,

						 divider->width,

						 divider->flags, val);

	}



	return divider_determine_rate(hw, req, divider->table, divider->width,

				      divider->flags);

}



int divider_get_val(unsigned long rate, unsigned long parent_rate,

		    const struct clk_div_table *table, u8 width,

		    unsigned long flags)
@@ -501,6 +522,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 
const struct clk_ops clk_divider_ops = {

	.recalc_rate = clk_divider_recalc_rate,

	.round_rate = clk_divider_round_rate,

	.determine_rate = clk_divider_determine_rate,

	.set_rate = clk_divider_set_rate,

};

EXPORT_SYMBOL_GPL(clk_divider_ops);
@@ -508,6 +530,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops); 
const struct clk_ops clk_divider_ro_ops = {

	.recalc_rate = clk_divider_recalc_rate,

	.round_rate = clk_divider_round_rate,

	.determine_rate = clk_divider_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_divider_ro_ops);

drivers/clk/clk-palmas.c

+1 −9
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Clock driver for Palmas device.

 *
@@ -6,15 +7,6 @@ 
 *

 * Author:	Laxman Dewangan <ldewangan@nvidia.com>

 *		Peter Ujfalusi <peter.ujfalusi@ti.com>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,

 * whether express or implied; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU

 * General Public License for more details.

 */



#include <linux/clk.h>

drivers/clk/clk-stm32f4.c

+4 −4
Original line number Diff line number Diff line
@@ -709,10 +709,10 @@ static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw, 
	return clk_divider_ops.recalc_rate(hw, parent_rate);

}



static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long *prate)

static int stm32f4_pll_div_determine_rate(struct clk_hw *hw,

					  struct clk_rate_request *req)

{

	return clk_divider_ops.round_rate(hw, rate, prate);

	return clk_divider_ops.determine_rate(hw, req);

}



static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -738,7 +738,7 @@ static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops stm32f4_pll_div_ops = {

	.recalc_rate = stm32f4_pll_div_recalc_rate,

	.round_rate = stm32f4_pll_div_round_rate,

	.determine_rate = stm32f4_pll_div_determine_rate,

	.set_rate = stm32f4_pll_div_set_rate,

};

drivers/clk/clk-stm32h7.c

+4 −4
Original line number Diff line number Diff line
@@ -845,10 +845,10 @@ static unsigned long odf_divider_recalc_rate(struct clk_hw *hw, 
	return clk_divider_ops.recalc_rate(hw, parent_rate);

}



static long odf_divider_round_rate(struct clk_hw *hw, unsigned long rate,

		unsigned long *prate)

static int odf_divider_determine_rate(struct clk_hw *hw,

				      struct clk_rate_request *req)

{

	return clk_divider_ops.round_rate(hw, rate, prate);

	return clk_divider_ops.determine_rate(hw, req);

}



static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -875,7 +875,7 @@ static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate, 


static const struct clk_ops odf_divider_ops = {

	.recalc_rate	= odf_divider_recalc_rate,

	.round_rate	= odf_divider_round_rate,

	.determine_rate	= odf_divider_determine_rate,

	.set_rate	= odf_divider_set_rate,

};