Commit 4990d8c1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-qcom', 'clk-socfpga', 'clk-mediatek', 'clk-lmk' and 'clk-x86' into clk-next 

 - Support video, gpu, display clks on qcom sc7280 SoCs
 - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
 - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
 - Migrate to clk_parent_data in gcc-sdm660
 - RPMh clks on qcom SM6350 SoCs
 - Support for Mediatek MT8192 SoCs

* clk-qcom: (38 commits)
  clk: qcom: Add SM6350 GCC driver
  dt-bindings: clock: Add SM6350 GCC clock bindings
  clk: qcom: rpmh: Add support for RPMH clocks on SM6350
  dt-bindings: clock: Add RPMHCC bindings for SM6350
  clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250
  clk: qcom: Add Global Clock controller (GCC) driver for SM6115
  dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC
  clk: qcom: mmcc-msm8994: Add MSM8992 support
  clk: qcom: Add msm8994 MMCC driver
  dt-bindings: clock: Add support for MSM8992/4 MMCC
  clk: qcom: Add Global Clock Controller driver for MSM8953
  dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings
  clk: qcom: gcc-sdm660: Replace usage of parent_names
  clk: qcom: gcc-sdm660: Move parent tables after PLLs
  clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create
  PM: runtime: add devm_pm_clk_create helper
  PM: runtime: add devm_pm_runtime_enable helper
  clk: qcom: a53-pll: Add MSM8939 a53pll support
  dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support
  clk: qcom: a53pll/mux: Use unique clock name
  ...

* clk-socfpga:
  clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
  clk: socfpga: agilex: fix up s2f_user0_clk representation
  clk: socfpga: agilex: fix the parents of the psi_ref_clk

* clk-mediatek: (22 commits)
  clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167
  clk: mediatek: Add MT8192 vencsys clock support
  clk: mediatek: Add MT8192 vdecsys clock support
  clk: mediatek: Add MT8192 scp adsp clock support
  clk: mediatek: Add MT8192 msdc clock support
  clk: mediatek: Add MT8192 mmsys clock support
  clk: mediatek: Add MT8192 mfgcfg clock support
  clk: mediatek: Add MT8192 mdpsys clock support
  clk: mediatek: Add MT8192 ipesys clock support
  clk: mediatek: Add MT8192 imp i2c wrapper clock support
  clk: mediatek: Add MT8192 imgsys clock support
  clk: mediatek: Add MT8192 camsys clock support
  clk: mediatek: Add MT8192 audio clock support
  clk: mediatek: Add MT8192 basic clocks support
  clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
  clk: mediatek: Add configurable enable control to mtk_pll_data
  clk: mediatek: Fix asymmetrical PLL enable and disable control
  clk: mediatek: Get regmap without syscon compatible check
  clk: mediatek: Add dt-bindings of MT8192 clocks
  dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192
  ...

* clk-lmk:
  clk: lmk04832: drop redundant fallthrough statements

* clk-x86:
  clk: x86: Rename clk-lpt to more specific clk-lpss-atom
parents 2734d6c1 131abae9 d17929eb d17e4e62 284c537a cf0a9565

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ Required Properties: 
	- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"

	- "mediatek,mt8167-audiosys", "syscon"

	- "mediatek,mt8183-audiosys", "syscon"

	- "mediatek,mt8192-audsys", "syscon"

	- "mediatek,mt8516-audsys", "syscon"

- #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ Required Properties: 
	- "mediatek,mt8167-mmsys", "syscon"

	- "mediatek,mt8173-mmsys", "syscon"

	- "mediatek,mt8183-mmsys", "syscon"

	- "mediatek,mt8192-mmsys", "syscon"

- #clock-cells: Must be 1



For the clock control, the mmsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml

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+199 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek Functional Clock Controller for MT8192



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The Mediatek functional clock controller provides various clocks on MT8192.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8192-scp_adsp

          - mediatek,mt8192-imp_iic_wrap_c

          - mediatek,mt8192-imp_iic_wrap_e

          - mediatek,mt8192-imp_iic_wrap_s

          - mediatek,mt8192-imp_iic_wrap_ws

          - mediatek,mt8192-imp_iic_wrap_w

          - mediatek,mt8192-imp_iic_wrap_n

          - mediatek,mt8192-msdc_top

          - mediatek,mt8192-msdc

          - mediatek,mt8192-mfgcfg

          - mediatek,mt8192-imgsys

          - mediatek,mt8192-imgsys2

          - mediatek,mt8192-vdecsys_soc

          - mediatek,mt8192-vdecsys

          - mediatek,mt8192-vencsys

          - mediatek,mt8192-camsys

          - mediatek,mt8192-camsys_rawa

          - mediatek,mt8192-camsys_rawb

          - mediatek,mt8192-camsys_rawc

          - mediatek,mt8192-ipesys

          - mediatek,mt8192-mdpsys



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    scp_adsp: clock-controller@10720000 {

        compatible = "mediatek,mt8192-scp_adsp";

        reg = <0x10720000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_c: clock-controller@11007000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_c";

        reg = <0x11007000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_e: clock-controller@11cb1000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_e";

        reg = <0x11cb1000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_s: clock-controller@11d03000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_s";

        reg = <0x11d03000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_ws: clock-controller@11d23000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_ws";

        reg = <0x11d23000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_w: clock-controller@11e01000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_w";

        reg = <0x11e01000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imp_iic_wrap_n: clock-controller@11f02000 {

        compatible = "mediatek,mt8192-imp_iic_wrap_n";

        reg = <0x11f02000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    msdc_top: clock-controller@11f10000 {

        compatible = "mediatek,mt8192-msdc_top";

        reg = <0x11f10000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    msdc: clock-controller@11f60000 {

        compatible = "mediatek,mt8192-msdc";

        reg = <0x11f60000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    mfgcfg: clock-controller@13fbf000 {

        compatible = "mediatek,mt8192-mfgcfg";

        reg = <0x13fbf000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys: clock-controller@15020000 {

        compatible = "mediatek,mt8192-imgsys";

        reg = <0x15020000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    imgsys2: clock-controller@15820000 {

        compatible = "mediatek,mt8192-imgsys2";

        reg = <0x15820000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys_soc: clock-controller@1600f000 {

        compatible = "mediatek,mt8192-vdecsys_soc";

        reg = <0x1600f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vdecsys: clock-controller@1602f000 {

        compatible = "mediatek,mt8192-vdecsys";

        reg = <0x1602f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    vencsys: clock-controller@17000000 {

        compatible = "mediatek,mt8192-vencsys";

        reg = <0x17000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys: clock-controller@1a000000 {

        compatible = "mediatek,mt8192-camsys";

        reg = <0x1a000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawa: clock-controller@1a04f000 {

        compatible = "mediatek,mt8192-camsys_rawa";

        reg = <0x1a04f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawb: clock-controller@1a06f000 {

        compatible = "mediatek,mt8192-camsys_rawb";

        reg = <0x1a06f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    camsys_rawc: clock-controller@1a08f000 {

        compatible = "mediatek,mt8192-camsys_rawc";

        reg = <0x1a08f000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    ipesys: clock-controller@1b000000 {

        compatible = "mediatek,mt8192-ipesys";

        reg = <0x1b000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    mdpsys: clock-controller@1f000000 {

        compatible = "mediatek,mt8192-mdpsys";

        reg = <0x1f000000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: MediaTek System Clock Controller for MT8192



maintainers:

  - Chun-Jie Chen <chun-jie.chen@mediatek.com>



description:

  The Mediatek system clock controller provides various clocks and system configuration

  like reset and bus protection on MT8192.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8192-topckgen

          - mediatek,mt8192-infracfg

          - mediatek,mt8192-pericfg

          - mediatek,mt8192-apmixedsys

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    topckgen: syscon@10000000 {

        compatible = "mediatek,mt8192-topckgen", "syscon";

        reg = <0x10000000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    infracfg: syscon@10001000 {

        compatible = "mediatek,mt8192-infracfg", "syscon";

        reg = <0x10001000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    pericfg: syscon@10003000 {

        compatible = "mediatek,mt8192-pericfg", "syscon";

        reg = <0x10003000 0x1000>;

        #clock-cells = <1>;

    };



  - |

    apmixedsys: syscon@1000c000 {

        compatible = "mediatek,mt8192-apmixedsys", "syscon";

        reg = <0x1000c000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

+3 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties: 
    enum:

      - qcom,ipq6018-a53pll

      - qcom,msm8916-a53pll

      - qcom,msm8939-a53pll



  reg:

    maxItems: 1
@@ -33,6 +34,8 @@ properties: 
    items:

      - const: xo



  operating-points-v2: true



required:

  - compatible

  - reg