Commit 6f7478e3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and 'clk-socfpga' into clk-next 

 - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
   MT8195 SoCs
 - Converted most Mediatek clock drivers to struct platform_driver
 - MediaTek clock drivers can be built as modules
 - Mediatek MT8188 SoC clk drivers
 - Clock driver for Sunplus SP7021 SoC
 - Reimplement Loongson-1 clk driver with DT support
 - Clk driver support for Loongson-2 SoCs
 - Migrate socfpga clk driver to of_clk_add_hw_provider()

* clk-mediatek: (84 commits)
  clk: mediatek: fhctl: Mark local variables static
  clk: mediatek: Use right match table, include mod_devicetable
  clk: mediatek: Add MT8188 adsp clock support
  clk: mediatek: Add MT8188 imp i2c wrapper clock support
  clk: mediatek: Add MT8188 wpesys clock support
  clk: mediatek: Add MT8188 vppsys1 clock support
  clk: mediatek: Add MT8188 vppsys0 clock support
  clk: mediatek: Add MT8188 vencsys clock support
  clk: mediatek: Add MT8188 vdosys1 clock support
  clk: mediatek: Add MT8188 vdosys0 clock support
  clk: mediatek: Add MT8188 vdecsys clock support
  clk: mediatek: Add MT8188 mfgcfg clock support
  clk: mediatek: Add MT8188 ipesys clock support
  clk: mediatek: Add MT8188 imgsys clock support
  clk: mediatek: Add MT8188 ccusys clock support
  clk: mediatek: Add MT8188 camsys clock support
  clk: mediatek: Add MT8188 infrastructure clock support
  clk: mediatek: Add MT8188 peripheral clock support
  clk: mediatek: Add MT8188 topckgen clock support
  clk: mediatek: Add MT8188 apmixedsys clock support
  ...

* clk-sunplus:
  clk: Add Sunplus SP7021 clock driver

* clk-loongson:
  clk: clk-loongson2: add clock controller driver support
  dt-bindings: clock: add loongson-2 boot clock index
  MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE
  MIPS: loongson32: Update the clock initialization
  clk: loongson1: Re-implement the clock driver
  clk: loongson1: Remove the outdated driver
  dt-bindings: clock: Add Loongson-1 clock

* clk-socfpga:
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling
  clk: socfpga: use of_clk_add_hw_provider and improve error handling
parents 4ec6a2f9 cb9eee59 d54c1fd4 acc0ccff 3dc6faa3

Documentation/devicetree/bindings/clock/loongson,ls1x-clk.yaml

0 → 100644
+45 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Loongson-1 Clock Controller



maintainers:

  - Keguang Zhang <keguang.zhang@gmail.com>



properties:

  compatible:

    enum:

      - loongson,ls1b-clk

      - loongson,ls1c-clk



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    clkc: clock-controller@1fe78030 {

        compatible = "loongson,ls1b-clk";

        reg = <0x1fe78030 0x8>;



        clocks = <&xtal>;

        #clock-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml

+6 −1
Original line number Diff line number Diff line
@@ -16,7 +16,12 @@ description: | 


properties:

  compatible:

    const: mediatek,mt8186-fhctl

    enum:

      - mediatek,mt6795-fhctl

      - mediatek,mt8173-fhctl

      - mediatek,mt8186-fhctl

      - mediatek,mt8192-fhctl

      - mediatek,mt8195-fhctl



  reg:

    maxItems: 1

Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml

0 → 100644
+71 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Functional Clock Controller for MT8188



maintainers:

  - Garmin Chang <garmin.chang@mediatek.com>



description: |

  The clock architecture in MediaTek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The devices provide clock gate control in different IP blocks.



properties:

  compatible:

    enum:

      - mediatek,mt8188-adsp-audio26m

      - mediatek,mt8188-camsys

      - mediatek,mt8188-camsys-rawa

      - mediatek,mt8188-camsys-rawb

      - mediatek,mt8188-camsys-yuva

      - mediatek,mt8188-camsys-yuvb

      - mediatek,mt8188-ccusys

      - mediatek,mt8188-imgsys

      - mediatek,mt8188-imgsys-wpe1

      - mediatek,mt8188-imgsys-wpe2

      - mediatek,mt8188-imgsys-wpe3

      - mediatek,mt8188-imgsys1-dip-nr

      - mediatek,mt8188-imgsys1-dip-top

      - mediatek,mt8188-imp-iic-wrap-c

      - mediatek,mt8188-imp-iic-wrap-en

      - mediatek,mt8188-imp-iic-wrap-w

      - mediatek,mt8188-ipesys

      - mediatek,mt8188-mfgcfg

      - mediatek,mt8188-vdecsys

      - mediatek,mt8188-vdecsys-soc

      - mediatek,mt8188-vencsys

      - mediatek,mt8188-vppsys0

      - mediatek,mt8188-vppsys1

      - mediatek,mt8188-wpesys

      - mediatek,mt8188-wpesys-vpp0



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@11283000 {

        compatible = "mediatek,mt8188-imp-iic-wrap-c";

        reg = <0x11283000 0x1000>;

        #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml

0 → 100644
+55 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek System Clock Controller for MT8188



maintainers:

  - Garmin Chang <garmin.chang@mediatek.com>



description: |

  The clock architecture in MediaTek like below

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The apmixedsys provides most of PLLs which generated from SoC 26m.

  The topckgen provides dividers and muxes which provide the clock source to other IP blocks.

  The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.

  The mcusys provides mux control to select the clock source in AP MCU.

  The device nodes also provide the system control capacity for configuration.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8188-apmixedsys

          - mediatek,mt8188-infracfg-ao

          - mediatek,mt8188-pericfg-ao

          - mediatek,mt8188-topckgen

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    clock-controller@10000000 {

        compatible = "mediatek,mt8188-topckgen", "syscon";

        reg = <0x10000000 0x1000>;

        #clock-cells = <1>;

    };

MAINTAINERS

+2 −1
Original line number Diff line number Diff line
@@ -2849,6 +2849,7 @@ F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml 
F:	arch/arm/boot/dts/sunplus-sp7021*.dts*

F:	arch/arm/configs/sp7021_*defconfig

F:	arch/arm/mach-sunplus/

F:	drivers/clk/clk-sp7021.c

F:	drivers/irqchip/irq-sp7021-intc.c

F:	drivers/reset/reset-sunplus.c

F:	include/dt-bindings/clock/sunplus,sp7021-clkc.h
@@ -12121,6 +12122,7 @@ M: Yinbo Zhu <zhuyinbo@loongson.cn> 
L:	linux-clk@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml

F:	drivers/clk/clk-loongson2.c

F:	include/dt-bindings/clock/loongson,ls2k-clk.h









LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)








@@ -14000,7 +14002,6 @@ L:	linux-mips@vger.kernel.org







S:	Maintained









F:	arch/mips/include/asm/mach-loongson32/









F:	arch/mips/loongson32/









F:	drivers/*/*/*loongson1*









F:	drivers/*/*loongson1*

















MIPS/LOONGSON2EF ARCHITECTURE