Commit 6f6869dc authored by Hamza Mahfooz's avatar Hamza Mahfooz Committed by Alex Deucher
Browse files

drm/amd/display: prep work for root clock optimization enablement for DCN314 



To enable root clock optimizations, we need a number of
register writes and need to account for the difference
in DPSTREAMCLK between DCN31 and DCN314. To prevent
issues, add a number of register writes to
DCCG_MASK_SH_LIST_DCN314_COMMON(), and define dccg314_init()
which is mostly in alignment with dccg31_init() but
accounts for the new DPSTREAMCLK sequence.

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0efa7035

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c

+27 −1
Original line number Diff line number Diff line
@@ -274,6 +274,32 @@ static void dccg314_set_dpstreamclk( 
	}

}



void dccg314_init(struct dccg *dccg)

{

	int otg_inst;



	/* Set HPO stream encoder to use refclk to avoid case where PHY is

	 * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which

	 * will cause DCN to hang.

	 */

	for (otg_inst = 0; otg_inst < 4; otg_inst++)

		dccg31_disable_symclk32_se(dccg, otg_inst);



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)

		for (otg_inst = 0; otg_inst < 2; otg_inst++)

			dccg31_disable_symclk32_le(dccg, otg_inst);



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)

		for (otg_inst = 0; otg_inst < 4; otg_inst++)

			dccg314_set_dpstreamclk(dccg, REFCLK, otg_inst,

						otg_inst);



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk)

		for (otg_inst = 0; otg_inst < 5; otg_inst++)

			dccg31_set_physymclk(dccg, otg_inst,

					     PHYSYMCLK_FORCE_SRC_SYMCLK, false);

}



static void dccg314_set_valid_pixel_rate(

		struct dccg *dccg,

		int ref_dtbclk_khz,
@@ -315,7 +341,7 @@ static const struct dccg_funcs dccg314_funcs = { 
	.update_dpp_dto = dccg31_update_dpp_dto,

	.dpp_root_clock_control = dccg314_dpp_root_clock_control,

	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,

	.dccg_init = dccg31_init,

	.dccg_init = dccg314_init,

	.set_dpstreamclk = dccg314_set_dpstreamclk,

	.enable_symclk32_se = dccg31_enable_symclk32_se,

	.disable_symclk32_se = dccg31_disable_symclk32_se,

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.h

+6 −0
Original line number Diff line number Diff line
@@ -155,6 +155,12 @@ 
	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\

	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\

	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)