Commit 0efa7035 authored by Zhikai Zhai's avatar Zhikai Zhai Committed by Alex Deucher
Browse files

drm/amd/display: add scaler control for dcn32 



[WHY]
It will introduce the extra warnning log on some asic
that doesn't register

[HOW]
Add the register on dcn32

Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarZhikai Zhai <zhikai.zhai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent abaeafb1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h

+1 −0
Original line number Diff line number Diff line
@@ -472,6 +472,7 @@ double dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *conte 
      SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id),          \

      SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id),          \

      SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id),      \

      SRI_ARR(DSCL_CONTROL, DSCL, id),                                         \

      SRI_ARR(SCL_TAP_CONTROL, DSCL, id),                                      \

      SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id),                              \

      SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id),                                \