Commit 6f6583e5 authored by Muhammad Ahmed's avatar Muhammad Ahmed Committed by Alex Deucher
Browse files

drm/amd/display: Fix MST recognizes connected displays as one 



[What]
MST now recognizes both connected displays

Fixes: 927e784c ("drm/amd/display: Add symclk enable/disable during stream enable/disable")
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarMuhammad Ahmed <ahmed.ahmed@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce9ecca0

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+17 −13
Original line number Diff line number Diff line
@@ -1178,12 +1178,15 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
		dto_params.otg_inst = tg->inst;

		dto_params.timing = &pipe_ctx->stream->timing;

		dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

		if (dccg) {

			dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

			dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

			dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

	} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se)

		}

	} else if (dccg && dccg->funcs->disable_symclk_se) {

		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

				link_enc->transmitter - TRANSMITTER_UNIPHY_A);

	}



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		/* TODO: This looks like a bug to me as we are disabling HPO IO when
@@ -2658,7 +2661,7 @@ void dce110_prepare_bandwidth( 
	struct clk_mgr *dccg = dc->clk_mgr;



	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);



	if (dccg)

		dccg->funcs->update_clocks(

				dccg,

				context,
@@ -2673,6 +2676,7 @@ void dce110_optimize_bandwidth( 


	dce110_set_displaymarks(dc, context);



	if (dccg)

		dccg->funcs->update_clocks(

				dccg,

				context,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+2 −6
Original line number Diff line number Diff line
@@ -2692,8 +2692,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
	struct dce_hwseq *hws = dc->hwseq;

	unsigned int k1_div = PIXEL_RATE_DIV_NA;

	unsigned int k2_div = PIXEL_RATE_DIV_NA;

	struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);

	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		if (dc->hwseq->funcs.setup_hpo_hw_control)
@@ -2713,10 +2711,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
		dto_params.timing = &pipe_ctx->stream->timing;

		dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

	} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se)

		dccg->funcs->enable_symclk_se(dccg,

			stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);



	} else {

		}

	if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {

		hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ void mpc32_power_on_blnd_lut( 
		if (power_on) {

			REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);

			REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);

		} else {

		} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {

			ASSERT(false);

			/* TODO: change to mpc

			 *  dpp_base->ctx->dc->optimized_required = true;