Commit 6f07707f authored by Vandita Kulkarni's avatar Vandita Kulkarni
Browse files

drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB 



v2: Fix the typo, move out the hardcoding from
    macro(Jani, Ville)

Fixes: f87c46c4 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211019151435.20477-2-vandita.kulkarni@intel.com
parent 2a2d23b6

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −1
Original line number Diff line number Diff line
@@ -1269,7 +1269,8 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder) 
	if (DISPLAY_VER(i915) == 13) {

		for_each_dsi_port(port, intel_dsi->ports)

			intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),

				     TGL_DSI_CHKN_LSHS_GB, 0x4);

				     TGL_DSI_CHKN_LSHS_GB_MASK,

				     TGL_DSI_CHKN_LSHS_GB(4));

	}

}

drivers/gpu/drm/i915/i915_reg.h

+3 −1
Original line number Diff line number Diff line
@@ -11730,7 +11730,9 @@ enum skl_power_gate { 
#define TGL_DSI_CHKN_REG(port)		_MMIO_PORT(port,	\

						    _TGL_DSI_CHKN_REG_0, \

						    _TGL_DSI_CHKN_REG_1)

#define TGL_DSI_CHKN_LSHS_GB			REG_GENMASK(15, 12)

#define TGL_DSI_CHKN_LSHS_GB_MASK		REG_GENMASK(15, 12)

#define TGL_DSI_CHKN_LSHS_GB(byte_clocks)	REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \

							       (byte_clocks))









/* Display Stream Splitter Control */









#define DSS_CTL1				_MMIO(0x67400)