Commit f87c46c4 authored by Vandita Kulkarni's avatar Vandita Kulkarni
Browse files

drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband 



Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband"
field to account for the repeaters on the HS Request/Ready PPI signaling
between the Display engine and the DPHY.

v2: Fix build issue.
v3: Align to new naming (Jani)

Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210826054811.10572-2-vandita.kulkarni@intel.com
parent f7a8f9af

drivers/gpu/drm/i915/display/icl_dsi.c

+23 −0
Original line number Diff line number Diff line
@@ -1271,6 +1271,26 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder, 
			     IGNORE_KVMR_PIPE_A,

			     enable ? IGNORE_KVMR_PIPE_A : 0);

}



/*

 * Wa_16012360555:adl-p

 * SW will have to program the "LP to HS Wakeup Guardband"

 * to account for the repeaters on the HS Request/Ready

 * PPI signaling between the Display engine and the DPHY.

 */

static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	enum port port;



	if (DISPLAY_VER(i915) == 13) {

		for_each_dsi_port(port, intel_dsi->ports)

			intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),

				     TGL_DSI_CHKN_LSHS_GB, 0x4);

	}

}



static void gen11_dsi_enable(struct intel_atomic_state *state,

			     struct intel_encoder *encoder,

			     const struct intel_crtc_state *crtc_state,
@@ -1284,6 +1304,9 @@ static void gen11_dsi_enable(struct intel_atomic_state *state, 
	/* Wa_1409054076:icl,jsl,ehl */

	icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);



	/* Wa_16012360555:adl-p */

	adlp_set_lp_hs_wakeup_gb(encoder);



	/* step6d: enable dsi transcoder */

	gen11_dsi_enable_transcoder(encoder);

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -11628,6 +11628,14 @@ enum skl_power_gate { 
						    _ICL_DSI_IO_MODECTL_1)

#define  COMBO_PHY_MODE_DSI				(1 << 0)



/* TGL DSI Chicken register */

#define _TGL_DSI_CHKN_REG_0			0x6B0C0

#define _TGL_DSI_CHKN_REG_1			0x6B8C0

#define TGL_DSI_CHKN_REG(port)		_MMIO_PORT(port,	\

						    _TGL_DSI_CHKN_REG_0, \

						    _TGL_DSI_CHKN_REG_1)

#define TGL_DSI_CHKN_LSHS_GB			REG_GENMASK(15, 12)



/* Display Stream Splitter Control */

#define DSS_CTL1				_MMIO(0x67400)

#define  SPLITTER_ENABLE			(1 << 31)