irqchip/gic-v3-its: introduce CONFIG_GENERIC_PENDING_IRQ

hulk inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6BO2R


CVE: NA

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Now, There is some issues about LPI migration on ARM SMP platform.

For example, NIC device generates MSI and sends LPI to CPU0 via ITS,
meanwhile irqbalance running on CPU1 set irq affinty of NIC to CPU1,
the next interrupt will be sent to CPU2, due to the state of irq is
still in progress, kernel does not end up performing irq handler on
CPU2, which results in some userland service timeouts, the sequence
of events is shown as follows:

NIC			CPU0			CPU1

Generate IRQ#1		READ_IAR
			Lock irq_desc
			Set IRQD_IN_PROGRESS
			Unlock irq_desc
						Lock irq_desc
						Change LPI Affinity
						Unlock irq_desc
			Call irq_handler
Generate IRQ#2
						READ_IAR
						Lock irq_desc
						Check IRQD_IN_PROGRESS
						Unlock irq_desc
						Return from interrupt#2
			Lock irq_desc
			Clear IRQD_IN_PROGRESS
			Unlock irq_desc
			return from interrupt#1

For this scenario, We can enable CONFIG_GENERIC_PENDING_IRQ to avoid this.

The CONFIG_GENERIC_PENDING_IRQ will delay all action that modify LPI
affinity until the next interrupt eoi handler.

Signed-off-by: Yipeng Zou <zouyipeng@huawei.com>
Reviewed-by: Liao Chang <liaochang1@huawei.com>
Reviewed-by: Zhang Jianhua <chris.zjh@huawei.com>
Signed-off-by: Yongqiang Liu <liuyongqiang13@huawei.com>