Loading drivers/gpu/drm/radeon/cik.c +21 −0 Original line number Diff line number Diff line Loading @@ -78,6 +78,27 @@ extern void si_rlc_fini(struct radeon_device *rdev); extern int si_rlc_init(struct radeon_device *rdev); static void cik_rlc_stop(struct radeon_device *rdev); /* * Indirect registers accessor */ u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg) { u32 r; WREG32(PCIE_INDEX, reg); (void)RREG32(PCIE_INDEX); r = RREG32(PCIE_DATA); return r; } void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) { WREG32(PCIE_INDEX, reg); (void)RREG32(PCIE_INDEX); WREG32(PCIE_DATA, v); (void)RREG32(PCIE_DATA); } /** * cik_get_xclk - get the xclk * Loading drivers/gpu/drm/radeon/cikd.h +3 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,9 @@ #define CG_CLKPIN_CNTL 0xC05001A0 # define XTALIN_DIVIDE (1 << 1) #define PCIE_INDEX 0x38 #define PCIE_DATA 0x3C #define VGA_HDP_CONTROL 0x328 #define VGA_MEMORY_DISABLE (1 << 4) Loading drivers/gpu/drm/radeon/radeon_asic.c +5 −1 Original line number Diff line number Diff line Loading @@ -126,7 +126,11 @@ static void radeon_register_accessor_init(struct radeon_device *rdev) rdev->mc_rreg = &rs780_mc_rreg; rdev->mc_wreg = &rs780_mc_wreg; } if (rdev->family >= CHIP_R600) { if (rdev->family >= CHIP_BONAIRE) { rdev->pciep_rreg = &cik_pciep_rreg; rdev->pciep_wreg = &cik_pciep_wreg; } else if (rdev->family >= CHIP_R600) { rdev->pciep_rreg = &r600_pciep_rreg; rdev->pciep_wreg = &r600_pciep_wreg; } Loading drivers/gpu/drm/radeon/radeon_asic.h +2 −0 Original line number Diff line number Diff line Loading @@ -558,5 +558,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); */ uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); u32 cik_get_xclk(struct radeon_device *rdev); uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); #endif Loading
drivers/gpu/drm/radeon/cik.c +21 −0 Original line number Diff line number Diff line Loading @@ -78,6 +78,27 @@ extern void si_rlc_fini(struct radeon_device *rdev); extern int si_rlc_init(struct radeon_device *rdev); static void cik_rlc_stop(struct radeon_device *rdev); /* * Indirect registers accessor */ u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg) { u32 r; WREG32(PCIE_INDEX, reg); (void)RREG32(PCIE_INDEX); r = RREG32(PCIE_DATA); return r; } void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) { WREG32(PCIE_INDEX, reg); (void)RREG32(PCIE_INDEX); WREG32(PCIE_DATA, v); (void)RREG32(PCIE_DATA); } /** * cik_get_xclk - get the xclk * Loading
drivers/gpu/drm/radeon/cikd.h +3 −0 Original line number Diff line number Diff line Loading @@ -35,6 +35,9 @@ #define CG_CLKPIN_CNTL 0xC05001A0 # define XTALIN_DIVIDE (1 << 1) #define PCIE_INDEX 0x38 #define PCIE_DATA 0x3C #define VGA_HDP_CONTROL 0x328 #define VGA_MEMORY_DISABLE (1 << 4) Loading
drivers/gpu/drm/radeon/radeon_asic.c +5 −1 Original line number Diff line number Diff line Loading @@ -126,7 +126,11 @@ static void radeon_register_accessor_init(struct radeon_device *rdev) rdev->mc_rreg = &rs780_mc_rreg; rdev->mc_wreg = &rs780_mc_wreg; } if (rdev->family >= CHIP_R600) { if (rdev->family >= CHIP_BONAIRE) { rdev->pciep_rreg = &cik_pciep_rreg; rdev->pciep_wreg = &cik_pciep_wreg; } else if (rdev->family >= CHIP_R600) { rdev->pciep_rreg = &r600_pciep_rreg; rdev->pciep_wreg = &r600_pciep_wreg; } Loading
drivers/gpu/drm/radeon/radeon_asic.h +2 −0 Original line number Diff line number Diff line Loading @@ -558,5 +558,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); */ uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); u32 cik_get_xclk(struct radeon_device *rdev); uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); #endif