Commit 2c67912c authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add get_xclk() callback for CIK 



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1d5d0c34

drivers/gpu/drm/radeon/cik.c

+22 −0
Original line number Diff line number Diff line
@@ -78,6 +78,28 @@ extern void si_rlc_fini(struct radeon_device *rdev); 
extern int si_rlc_init(struct radeon_device *rdev);

static void cik_rlc_stop(struct radeon_device *rdev);



/**

 * cik_get_xclk - get the xclk

 *

 * @rdev: radeon_device pointer

 *

 * Returns the reference clock used by the gfx engine

 * (CIK).

 */

u32 cik_get_xclk(struct radeon_device *rdev)

{

        u32 reference_clock = rdev->clock.spll.reference_freq;



	if (rdev->flags & RADEON_IS_IGP) {

		if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)

			return reference_clock / 2;

	} else {

		if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)

			return reference_clock / 4;

	}

	return reference_clock;

}



#define BONAIRE_IO_MC_REGS_SIZE 36



static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =

drivers/gpu/drm/radeon/cikd.h

+7 −0
Original line number Diff line number Diff line
@@ -28,6 +28,13 @@ 


#define CIK_RB_BITMAP_WIDTH_PER_SH  2



/* SMC IND registers */

#define GENERAL_PWRMGT                                    0xC0200000

#       define GPU_COUNTER_CLK                            (1 << 15)



#define CG_CLKPIN_CNTL                                    0xC05001A0

#       define XTALIN_DIVIDE                              (1 << 1)



#define VGA_HDP_CONTROL  				0x328

#define		VGA_MEMORY_DISABLE				(1 << 4)

drivers/gpu/drm/radeon/radeon_asic.h

+1 −0
Original line number Diff line number Diff line
@@ -557,5 +557,6 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 
 * cik

 */

uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);

u32 cik_get_xclk(struct radeon_device *rdev);



#endif