Commit 6e11940a authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner',... 

Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next

 - Make clk_ops::determine_rate mandatory for muxes

* clk-renesas:
  clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()
  clk: renesas: mstp: Convert to readl_poll_timeout_atomic()
  clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
  iopoll: Do not use timekeeping in read_poll_timeout_atomic()
  iopoll: Call cpu_relax() in busy loops
  clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
  clk: renesas: r8a779a0: Add PWM clock

* clk-determine-rate: (71 commits)
  clk: sprd: composite: Simplify determine_rate implementation
  ASoC: tlv320aic32x4: pll: Remove impossible condition in clk_aic32x4_pll_determine_rate()
  clk: Fix best_parent_rate after moving code into a separate function
  clk: Forbid to register a mux without determine_rate
  ASoC: tlv320aic32x4: div: Switch to determine_rate
  ASoC: tlv320aic32x4: pll: Switch to determine_rate
  clk: tegra: super: Switch to determine_rate
  clk: tegra: periph: Switch to determine_rate
  clk: stm32: composite: Switch to determine_rate
  clk: st: flexgen: Switch to determine_rate
  clk: sprd: composite: Switch to determine_rate
  clk: ingenic: tcu: Switch to determine_rate
  clk: ingenic: cgu: Switch to determine_rate
  clk: imx: scu: Switch to determine_rate
  clk: da8xx: clk48: Switch to determine_rate
  clk: si5351: clkout: Switch to determine_rate
  clk: si5351: msynth: Switch to determine_rate
  clk: si5351: pll: Switch to determine_rate
  clk: si5341: Switch to determine_rate
  clk: cdce706: clkout: Switch to determine_rate
  ...

* clk-allwinner:
  clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux

* clk-samsung:
  clk: samsung: add CONFIG_OF dependency
  clk: samsung: Re-add support for Exynos4212 CPU clock
  clk: samsung: Add Exynos4212 compatible to CLKOUT driver
  dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible

* clk-amlogic:
  MAINTAINERS: repair pattern in ARM/Amlogic Meson SoC CLOCK FRAMEWORK
  clk: meson: pll: remove unneeded semicolon
  clk: meson: a1: Staticize rtc clk
  clk: meson: a1: add Amlogic A1 Peripherals clock controller driver
  clk: meson: a1: add Amlogic A1 PLL clock controller driver
  clk: meson: introduce new pll power-on sequence for A1 SoC family
  clk: meson: make pll rst bit as optional
  dt-bindings: clock: meson: add A1 Peripherals clock controller bindings
  dt-bindings: clock: meson: add A1 PLL clock controller bindings
parents e155a366 e90f15be 587dd448 29d70888 59374d08 93908609

Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml

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+73 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic A1 Peripherals Clock Control Unit



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Jian Hu <jian.hu@jian.hu.com>

  - Dmitry Rokosov <ddrokosov@sberdevices.ru>



properties:

  compatible:

    const: amlogic,a1-peripherals-clkc



  '#clock-cells':

    const: 1



  reg:

    maxItems: 1



  clocks:

    items:

      - description: input fixed pll div2

      - description: input fixed pll div3

      - description: input fixed pll div5

      - description: input fixed pll div7

      - description: input hifi pll

      - description: input oscillator (usually at 24MHz)



  clock-names:

    items:

      - const: fclk_div2

      - const: fclk_div3

      - const: fclk_div5

      - const: fclk_div7

      - const: hifi_pll

      - const: xtal



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@800 {

            compatible = "amlogic,a1-peripherals-clkc";

            reg = <0 0x800 0 0x104>;

            #clock-cells = <1>;

            clocks = <&clkc_pll CLKID_FCLK_DIV2>,

                     <&clkc_pll CLKID_FCLK_DIV3>,

                     <&clkc_pll CLKID_FCLK_DIV5>,

                     <&clkc_pll CLKID_FCLK_DIV7>,

                     <&clkc_pll CLKID_HIFI_PLL>,

                     <&xtal>;

            clock-names = "fclk_div2", "fclk_div3",

                          "fclk_div5", "fclk_div7",

                          "hifi_pll", "xtal";

        };

    };

Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic A1 PLL Clock Control Unit



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Jian Hu <jian.hu@jian.hu.com>

  - Dmitry Rokosov <ddrokosov@sberdevices.ru>



properties:

  compatible:

    const: amlogic,a1-pll-clkc



  '#clock-cells':

    const: 1



  reg:

    maxItems: 1



  clocks:

    items:

      - description: input fixpll_in

      - description: input hifipll_in



  clock-names:

    items:

      - const: fixpll_in

      - const: hifipll_in



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@7c80 {

            compatible = "amlogic,a1-pll-clkc";

            reg = <0 0x7c80 0 0x18c>;

            #clock-cells = <1>;

            clocks = <&clkc_periphs CLKID_FIXPLL_IN>,

                     <&clkc_periphs CLKID_HIFIPLL_IN>;

            clock-names = "fixpll_in", "hifipll_in";

        };

    };

Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ properties: 
          - samsung,exynos3250-cmu-dmc

          - samsung,exynos3250-cmu-isp

          - samsung,exynos4210-clock

          - samsung,exynos4212-clock

          - samsung,exynos4412-clock

          - samsung,exynos5250-clock

      - items:

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1888,6 +1888,7 @@ L: linux-amlogic@lists.infradead.org 
S:	Maintained

F:	Documentation/devicetree/bindings/clock/amlogic*

F:	drivers/clk/meson/

F:	include/dt-bindings/clock/amlogic,a1*

F:	include/dt-bindings/clock/gxbb*

F:	include/dt-bindings/clock/meson*
































drivers/clk/actions/owl-composite.c



+24
−11






























Original line number
Diff line number
Diff line







@@ -53,13 +53,19 @@ static int owl_comp_is_enabled(struct clk_hw *hw)







	return owl_gate_clk_is_enabled(common, &comp->gate_hw);









}



















static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,









				unsigned long *parent_rate)









static int owl_comp_div_determine_rate(struct clk_hw *hw,









				       struct clk_rate_request *req)









{









	struct owl_composite *comp = hw_to_owl_comp(hw);









	long rate;



















	return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,









					rate, parent_rate);









	rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,









					     req->rate, &req->best_parent_rate);









	if (rate < 0)









		return rate;



















	req->rate = rate;









	return 0;









}



















static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,








@@ -80,14 +86,20 @@ static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,







					rate, parent_rate);









}



















static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,









			unsigned long *parent_rate)









static int owl_comp_fact_determine_rate(struct clk_hw *hw,









					struct clk_rate_request *req)









{









	struct owl_composite *comp = hw_to_owl_comp(hw);









	long rate;



















	return owl_factor_helper_round_rate(&comp->common,









	rate = owl_factor_helper_round_rate(&comp->common,









					    &comp->rate.factor_hw,









					rate, parent_rate);









					    req->rate, &req->best_parent_rate);









	if (rate < 0)









		return rate;



















	req->rate = rate;









	return 0;









}



















static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,








@@ -152,7 +164,7 @@ const struct clk_ops owl_comp_div_ops = {







	.is_enabled	= owl_comp_is_enabled,



















	/* div_ops */









	.round_rate	= owl_comp_div_round_rate,









	.determine_rate	= owl_comp_div_determine_rate,









	.recalc_rate	= owl_comp_div_recalc_rate,









	.set_rate	= owl_comp_div_set_rate,









};








@@ -169,7 +181,7 @@ const struct clk_ops owl_comp_fact_ops = {







	.is_enabled	= owl_comp_is_enabled,



















	/* fact_ops */









	.round_rate	= owl_comp_fact_round_rate,









	.determine_rate	= owl_comp_fact_determine_rate,









	.recalc_rate	= owl_comp_fact_recalc_rate,









	.set_rate	= owl_comp_fact_set_rate,









};








@@ -189,6 +201,7 @@ const struct clk_ops owl_comp_fix_fact_ops = {

















const struct clk_ops owl_comp_pass_ops = {









	/* mux_ops */









	.determine_rate	= clk_hw_determine_rate_no_reparent,









	.get_parent	= owl_comp_get_parent,









	.set_parent	= owl_comp_set_parent,