Commit 59374d08 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.5' of... 

Merge tag 'samsung-clk-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

 - Re-add support for Exynos4212 clock controller because we are
   re-introducing the SoC in the mainline
 - Add CONFIG_OF dependency to solve some objtool warnings

* tag 'samsung-clk-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: add CONFIG_OF dependency
  clk: samsung: Re-add support for Exynos4212 CPU clock
  clk: samsung: Add Exynos4212 compatible to CLKOUT driver
  dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible
parents ac9a7868 2aac2d8b

Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ properties: 
          - samsung,exynos3250-cmu-dmc

          - samsung,exynos3250-cmu-isp

          - samsung,exynos4210-clock

          - samsung,exynos4212-clock

          - samsung,exynos4412-clock

          - samsung,exynos5250-clock

      - items:

drivers/clk/samsung/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ 
# Recent Exynos platforms should just select COMMON_CLK_SAMSUNG:

config COMMON_CLK_SAMSUNG

	bool "Samsung Exynos clock controller support" if COMPILE_TEST

	depends on OF

	select S3C64XX_COMMON_CLK if ARM && ARCH_S3C64XX

	select S5PV210_COMMON_CLK if ARM && ARCH_S5PV210

	select EXYNOS_3250_COMMON_CLK if ARM && SOC_EXYNOS3250

drivers/clk/samsung/clk-exynos-clkout.c

+3 −0
Original line number Diff line number Diff line
@@ -55,6 +55,9 @@ static const struct of_device_id exynos_clkout_ids[] = { 
	}, {

		.compatible = "samsung,exynos4210-pmu",

		.data = &exynos_clkout_exynos4,

	}, {

		.compatible = "samsung,exynos4212-pmu",

		.data = &exynos_clkout_exynos4,

	}, {

		.compatible = "samsung,exynos4412-pmu",

		.data = &exynos_clkout_exynos4,

drivers/clk/samsung/clk-exynos4.c

+39 −5
Original line number Diff line number Diff line
@@ -138,7 +138,8 @@ 
/* the exynos4 soc type */

enum exynos4_soc {

	EXYNOS4210,

	EXYNOS4X12,

	EXYNOS4212,

	EXYNOS4412,

};



/* list of PLLs to be registered */
@@ -1205,6 +1206,24 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { 
	{  0 },

};



static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {

	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },

	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },

	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },

	{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },

	{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },

	{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },

	{  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },

	{  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },

	{  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },

	{  0 },

};



#define E4412_CPU_DIV1(cores, hpm, copy)				\

		(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
@@ -1233,6 +1252,11 @@ static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = { 
			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),

};



static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

		CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d),

};



static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {

	CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,

			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
@@ -1326,11 +1350,15 @@ static void __init exynos4_clk_init(struct device_node *np, 
		samsung_clk_register_fixed_factor(ctx,

			exynos4x12_fixed_factor_clks,

			ARRAY_SIZE(exynos4x12_fixed_factor_clks));

		if (soc == EXYNOS4412)

			samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,

					ARRAY_SIZE(exynos4412_cpu_clks));

		else

			samsung_clk_register_cpu(ctx, exynos4212_cpu_clks,

					ARRAY_SIZE(exynos4212_cpu_clks));

	}



	if (soc == EXYNOS4X12)

	if (soc == EXYNOS4212 || soc == EXYNOS4412)

		exynos4x12_core_down_clock();



	samsung_clk_extended_sleep_init(reg_base,
@@ -1363,8 +1391,14 @@ static void __init exynos4210_clk_init(struct device_node *np) 
}

CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);



static void __init exynos4212_clk_init(struct device_node *np)

{

	exynos4_clk_init(np, EXYNOS4212);

}

CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);



static void __init exynos4412_clk_init(struct device_node *np)

{

	exynos4_clk_init(np, EXYNOS4X12);

	exynos4_clk_init(np, EXYNOS4412);

}

CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);