Commit 6df241aa authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Rob Herring
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dt-bindings: cache: andestech,ax45mp-cache: Fix unit address in example 



The unit address in the example does not match the reg property.
Correct the unit address to match reality.

Fixes: 3e7bf468 ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/7b93655219a6ad696dd3faa9f36fde6b094694a9.1696330005.git.geert+renesas@glider.be


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 5d007ffd

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

+1 −1
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ examples: 
  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    cache-controller@2010000 {

    cache-controller@13400000 {

        compatible = "andestech,ax45mp-cache", "cache";

        reg = <0x13400000 0x100000>;

        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;