Unverified Commit 3e7bf468 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Palmer Dabbelt
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dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller 



Add DT binding documentation for L2 cache controller found on RZ/Five SoC.

The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. The AX45MP core has an L2 cache controller, this patch
describes the L2 cache block.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230818135723.80612-5-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent b79f300c

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

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+81 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (C) 2023 Renesas Electronics Corp.

%YAML 1.2

---

$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Andestech AX45MP L2 Cache Controller



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  A level-2 cache (L2C) is used to improve the system performance by providing

  a large amount of cache line entries and reasonable access delays. The L2C

  is shared between cores, and a non-inclusive non-exclusive policy is used.



select:

  properties:

    compatible:

      contains:

        enum:

          - andestech,ax45mp-cache



  required:

    - compatible



properties:

  compatible:

    items:

      - const: andestech,ax45mp-cache

      - const: cache



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  cache-line-size:

    const: 64



  cache-level:

    const: 2



  cache-sets:

    const: 1024



  cache-size:

    enum: [131072, 262144, 524288, 1048576, 2097152]



  cache-unified: true



  next-level-cache: true



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts

  - cache-line-size

  - cache-level

  - cache-sets

  - cache-size

  - cache-unified



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    cache-controller@2010000 {

        compatible = "andestech,ax45mp-cache", "cache";

        reg = <0x13400000 0x100000>;

        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;

        cache-line-size = <64>;

        cache-level = <2>;

        cache-sets = <1024>;

        cache-size = <262144>;

        cache-unified;

    };