Commit 6c021d77 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: fix sm8450 CTL configuration 



Correct the CTL size on sm8450 platform. This fixes the incorrect merge
of sm8350 support, which unfortunately also touched the SM8450 setup.

Fixes: 0e91bcbb ("drm/msm/dpu: Add SM8350 to hw catalog")
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/519671/
Link: https://lore.kernel.org/r/20230123080818.3069266-1-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 31c31805

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+5 −5
Original line number Diff line number Diff line
@@ -972,31 +972,31 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = { 
	},

	{

	.name = "ctl_1", .id = CTL_1,

	.base = 0x16000, .len = 0x1e8,

	.base = 0x16000, .len = 0x204,

	.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,

	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),

	},

	{

	.name = "ctl_2", .id = CTL_2,

	.base = 0x17000, .len = 0x1e8,

	.base = 0x17000, .len = 0x204,

	.features = CTL_SC7280_MASK,

	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),

	},

	{

	.name = "ctl_3", .id = CTL_3,

	.base = 0x18000, .len = 0x1e8,

	.base = 0x18000, .len = 0x204,

	.features = CTL_SC7280_MASK,

	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),

	},

	{

	.name = "ctl_4", .id = CTL_4,

	.base = 0x19000, .len = 0x1e8,

	.base = 0x19000, .len = 0x204,

	.features = CTL_SC7280_MASK,

	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),

	},

	{

	.name = "ctl_5", .id = CTL_5,

	.base = 0x1a000, .len = 0x1e8,

	.base = 0x1a000, .len = 0x204,

	.features = CTL_SC7280_MASK,

	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),

	},