Commit 31c31805 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: add missing ubwc_swizzle setting to catalog 



Use the values from the vendor DTs to set ubwc_swizzle in the catalog.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/519662/
Link: https://lore.kernel.org/r/20230123062415.3027743-1-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent daa9a2ec

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+5 −0
Original line number Diff line number Diff line
@@ -582,6 +582,7 @@ static const struct dpu_mdp_cfg sm6115_mdp[] = { 
	.base = 0x0, .len = 0x494,

	.features = 0,

	.highest_bank_bit = 0x1,

	.ubwc_swizzle = 0x7,

	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

		.reg_off = 0x2ac, .bit_off = 0},

	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
@@ -595,6 +596,7 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { 
	.base = 0x0, .len = 0x494,

	.features = 0,

	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */

	.ubwc_swizzle = 0x6,

	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

			.reg_off = 0x2AC, .bit_off = 0},

	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
@@ -651,6 +653,7 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = { 
	.base = 0x0, .len = 0x494,

	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),

	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */

	.ubwc_swizzle = 0x6,

	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

			.reg_off = 0x2AC, .bit_off = 0},

	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
@@ -677,6 +680,7 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { 
	.name = "top_0", .id = MDP_TOP,

	.base = 0x0, .len = 0x2014,

	.highest_bank_bit = 0x1,

	.ubwc_swizzle = 0x6,

	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

		.reg_off = 0x2AC, .bit_off = 0},

	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
@@ -713,6 +717,7 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = { 
	.base = 0, .len = 0x494,

	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),

	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */

	.ubwc_swizzle = 0x6,

	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {

			.reg_off = 0x4330, .bit_off = 0},

	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {