Commit 6b562738 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

dt-binding: mtd: nand: Document the cs-gpios property 



To reach higher capacities, arrays of chips are now pretty common.
Unfortunately, most of the controllers have been designed a decade ago
and did not all anticipate the need for several chip-selects. The new
cs-gpios property allows to workaround this limitation by adding as many
GPIO chip-select as needed.

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20210510171800.27225-1-miquel.raynal@bootlin.com
parent 4edde603

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+17 −1
Original line number Diff line number Diff line
@@ -38,6 +38,17 @@ properties: 


  ranges: true



  cs-gpios:

    minItems: 1

    maxItems: 8

    description:

      Array of chip-select available to the controller. The first

      entries are a 1:1 mapping of the available chip-select on the

      NAND controller (even if they are not used). As many additional

      chip-select as needed may follow and should be phandles of GPIO

      lines. 'reg' entries of the NAND chip subnodes become indexes of

      this array when this property is present.



patternProperties:

  "^nand@[a-f0-9]$":

    type: object
@@ -164,14 +175,19 @@ examples: 
    nand-controller {

      #address-cells = <1>;

      #size-cells = <0>;

      cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */



      /* controller specific properties */



      nand@0 {

        reg = <0>;

        reg = <0>; /* Native CS */

        nand-use-soft-ecc-engine;

        nand-ecc-algo = "bch";



        /* controller specific properties */

      };



      nand@1 {

        reg = <1>; /* GPIO CS */

      };

    };