Commit 6ad931a2 authored by Lu Baolu's avatar Lu Baolu Committed by Joerg Roedel
Browse files

iommu/vt-d: Avoid unnecessary global DMA cache invalidation 



Some VT-d hardware implementations invalidate all DMA remapping hardware
translation caches as part of SRTP flow. The VT-d spec adds a ESRTPS
(Enhanced Set Root Table Pointer Support, section 11.4.2 in VT-d spec)
capability bit to indicate this. With this bit set, software has no need
to issue the global invalidation request.

Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Reviewed-by: default avatarKevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20220919062523.3438951-3-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent eb5b2011

drivers/iommu/intel/iommu.c

+7 −0
Original line number Diff line number Diff line
@@ -1239,6 +1239,13 @@ static void iommu_set_root_entry(struct intel_iommu *iommu) 


	raw_spin_unlock_irqrestore(&iommu->register_lock, flag);



	/*

	 * Hardware invalidates all DMA remapping hardware translation

	 * caches as part of SRTP flow.

	 */

	if (cap_esrtps(iommu->cap))

		return;



	iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);

	if (sm_supported(iommu))

		qi_flush_pasid_cache(iommu, 0, QI_PC_GLOBAL, 0);

drivers/iommu/intel/iommu.h

+1 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ 
/*

 * Decoding Capability Register

 */

#define cap_esrtps(c)		(((c) >> 63) & 1)

#define cap_esirtps(c)		(((c) >> 62) & 1)

#define cap_fl5lp_support(c)	(((c) >> 60) & 1)

#define cap_pi_support(c)	(((c) >> 59) & 1)