Commit 6a3fc8c3 authored by Peter Rosin's avatar Peter Rosin Committed by Claudiu Beznea
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ARM: at91: fix build for SAMA5D3 w/o L2 cache 



The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but
apparently not for the older SAMA5D3.

Solves a build-time regression with the following symptom:

sama5.c:(.init.text+0x48): undefined reference to `outer_cache'

Fixes: 3b5a7ca7 ("ARM: at91: setup outer cache .write_sec() callback if needed")
Signed-off-by: default avatarPeter Rosin <peda@axentia.se>
[claudiu.beznea: delete "At least not always." from commit description]
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/b7f8dacc-5e1f-0eb2-188e-3ad9a9f7613d@axentia.se
parent 40a2226e

arch/arm/mach-at91/sama5.c

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ static void sama5_l2c310_write_sec(unsigned long val, unsigned reg) 
static void __init sama5_secure_cache_init(void)

{

	sam_secure_init();

	if (sam_linux_is_optee_available())

	if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())

		outer_cache.write_sec = sama5_l2c310_write_sec;

}