Commit 6a3aaa2b authored by Adrián Larumbe's avatar Adrián Larumbe Committed by Steven Price
Browse files

drm/panfrost: Add specific register offset macros for JS and MMU AS 



Each Panfrost job has its own job slot and MMU address space set of
registers, which are selected with a job-specific index.

Turn the shift and stride used for selection of the right register set base
into a define rather than using magic numbers.

Signed-off-by: default avatarAdrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: default avatarAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: default avatarSteven Price <steven.price@arm.com>
Signed-off-by: default avatarSteven Price <steven.price@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220729144610.2105223-2-adrian.larumbe@collabora.com
parent ef8886f3

drivers/gpu/drm/panfrost/panfrost_regs.h

+24 −18
Original line number Diff line number Diff line
@@ -226,23 +226,25 @@ 
#define JOB_INT_MASK_DONE(j)		BIT(j)



#define JS_BASE				0x1800

#define JS_HEAD_LO(n)			(JS_BASE + ((n) * 0x80) + 0x00)

#define JS_HEAD_HI(n)			(JS_BASE + ((n) * 0x80) + 0x04)

#define JS_TAIL_LO(n)			(JS_BASE + ((n) * 0x80) + 0x08)

#define JS_TAIL_HI(n)			(JS_BASE + ((n) * 0x80) + 0x0c)

#define JS_AFFINITY_LO(n)		(JS_BASE + ((n) * 0x80) + 0x10)

#define JS_AFFINITY_HI(n)		(JS_BASE + ((n) * 0x80) + 0x14)

#define JS_CONFIG(n)			(JS_BASE + ((n) * 0x80) + 0x18)

#define JS_XAFFINITY(n)			(JS_BASE + ((n) * 0x80) + 0x1c)

#define JS_COMMAND(n)			(JS_BASE + ((n) * 0x80) + 0x20)

#define JS_STATUS(n)			(JS_BASE + ((n) * 0x80) + 0x24)

#define JS_HEAD_NEXT_LO(n)		(JS_BASE + ((n) * 0x80) + 0x40)

#define JS_HEAD_NEXT_HI(n)		(JS_BASE + ((n) * 0x80) + 0x44)

#define JS_AFFINITY_NEXT_LO(n)		(JS_BASE + ((n) * 0x80) + 0x50)

#define JS_AFFINITY_NEXT_HI(n)		(JS_BASE + ((n) * 0x80) + 0x54)

#define JS_CONFIG_NEXT(n)		(JS_BASE + ((n) * 0x80) + 0x58)

#define JS_COMMAND_NEXT(n)		(JS_BASE + ((n) * 0x80) + 0x60)

#define JS_FLUSH_ID_NEXT(n)		(JS_BASE + ((n) * 0x80) + 0x70)

#define JS_SLOT_STRIDE			0x80



#define JS_HEAD_LO(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x00)

#define JS_HEAD_HI(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x04)

#define JS_TAIL_LO(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x08)

#define JS_TAIL_HI(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x0c)

#define JS_AFFINITY_LO(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x10)

#define JS_AFFINITY_HI(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x14)

#define JS_CONFIG(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x18)

#define JS_XAFFINITY(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x1c)

#define JS_COMMAND(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x20)

#define JS_STATUS(n)			(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x24)

#define JS_HEAD_NEXT_LO(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x40)

#define JS_HEAD_NEXT_HI(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x44)

#define JS_AFFINITY_NEXT_LO(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x50)

#define JS_AFFINITY_NEXT_HI(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x54)

#define JS_CONFIG_NEXT(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x58)

#define JS_COMMAND_NEXT(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x60)

#define JS_FLUSH_ID_NEXT(n)		(JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x70)



/* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */

#define JS_CONFIG_START_FLUSH_CLEAN		BIT(8)
@@ -281,7 +283,9 @@ 
#define AS_COMMAND_FLUSH_MEM		0x05	/* Wait for memory accesses to complete, flush all the L1s cache then

						   flush all L2 caches then issue a flush region command to all MMUs */



#define MMU_AS(as)			(0x2400 + ((as) << 6))

#define MMU_BASE			0x2400

#define MMU_AS_SHIFT			0x06

#define MMU_AS(as)			(MMU_BASE + ((as) << MMU_AS_SHIFT))



#define AS_TRANSTAB_LO(as)		(MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */

#define AS_TRANSTAB_HI(as)		(MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
@@ -300,6 +304,8 @@ 
#define AS_FAULTEXTRA_LO(as)		(MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */

#define AS_FAULTEXTRA_HI(as)		(MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */



#define MMU_AS_STRIDE			(1 << MMU_AS_SHIFT)



/*

 * Begin LPAE MMU TRANSTAB register values

 */