Commit 66efff51 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.2-2022-12-07' of https://gitlab.freedesktop.org/agd5f/linux into drm-next 



amd-drm-next-6.2-2022-12-07:

amdgpu:
- DSC fixes for DCN 2.1
- HDMI PCON fixes
- PSR fixes
- DC DML fixes
- Properly throttle on BO allocation
- GFX 11.0.4 fixes
- MMHUB fix
- Make some functions static

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221207232439.5908-1-alexander.deucher@amd.com
parents 9e5737bd 347fafe0

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+3 −13
Original line number Diff line number Diff line
@@ -113,7 +113,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 
	bp.resv = resv;

	bp.preferred_domain = initial_domain;

	bp.flags = flags;

	bp.domain = initial_domain;

	bp.domain = initial_domain | AMDGPU_GEM_DOMAIN_CPU;

	bp.bo_ptr_size = sizeof(struct amdgpu_bo);



	r = amdgpu_bo_create_user(adev, &bp, &ubo);
@@ -332,20 +332,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 
	}



	initial_domain = (u32)(0xffffffff & args->in.domains);

retry:

	r = amdgpu_gem_object_create(adev, size, args->in.alignment,

				     initial_domain,

				     flags, ttm_bo_type_device, resv, &gobj);

				     initial_domain, flags, ttm_bo_type_device,

				     resv, &gobj);

	if (r && r != -ERESTARTSYS) {

		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {

			flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;

			goto retry;

		}



		if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {

			initial_domain |= AMDGPU_GEM_DOMAIN_GTT;

			goto retry;

		}

		DRM_DEBUG("Failed to allocate GEM object (%llu, %d, %llu, %d)\n",

				size, initial_domain, args->in.alignment, r);

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+1 −0
Original line number Diff line number Diff line
@@ -549,6 +549,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) 
	/* YELLOW_CARP*/

	case IP_VERSION(10, 3, 3):

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 4):

		/* Don't enable it by default yet.

		 */

		if (amdgpu_tmz < 1) {

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+1 −5
Original line number Diff line number Diff line
@@ -581,10 +581,6 @@ int amdgpu_bo_create(struct amdgpu_device *adev, 
		bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;



	bo->tbo.bdev = &adev->mman.bdev;

	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |

			  AMDGPU_GEM_DOMAIN_GDS))

		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);

	else

	amdgpu_bo_placement_from_domain(bo, bp->domain);

	if (bp->type == ttm_bo_type_kernel)

		bo->tbo.priority = 1;

drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c

+3 −5
Original line number Diff line number Diff line
@@ -350,7 +350,7 @@ unsigned int amdgpu_sw_ring_priority(int idx) 
}



/*Scan on low prio rings to have unsignaled fence and high ring has no fence.*/

int amdgpu_mcbp_scan(struct amdgpu_ring_mux *mux)

static int amdgpu_mcbp_scan(struct amdgpu_ring_mux *mux)

{

	struct amdgpu_ring *ring;

	int i, need_preempt;
@@ -370,7 +370,7 @@ int amdgpu_mcbp_scan(struct amdgpu_ring_mux *mux) 
}



/* Trigger Mid-Command Buffer Preemption (MCBP) and find if we need to resubmit. */

int amdgpu_mcbp_trigger_preempt(struct amdgpu_ring_mux *mux)

static int amdgpu_mcbp_trigger_preempt(struct amdgpu_ring_mux *mux)

{

	int r;
@@ -434,7 +434,7 @@ void amdgpu_ring_mux_start_ib(struct amdgpu_ring_mux *mux, struct amdgpu_ring *r 


static void scan_and_remove_signaled_chunk(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring)

{

	uint32_t last_seq, size = 0;

	uint32_t last_seq = 0;

	struct amdgpu_mux_entry *e;

	struct amdgpu_mux_chunk *chunk, *tmp;
@@ -450,8 +450,6 @@ static void scan_and_remove_signaled_chunk(struct amdgpu_ring_mux *mux, struct a 
		if (chunk->sync_seq <= last_seq) {

			list_del(&chunk->entry);

			kmem_cache_free(amdgpu_mux_chunk_slab, chunk);

		} else {

			size++;

		}

	}

}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+3 −0
Original line number Diff line number Diff line
@@ -5058,6 +5058,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) 
	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {

		switch (adev->ip_versions[GC_HWIP][0]) {

		case IP_VERSION(11, 0, 1):

		case IP_VERSION(11, 0, 4):

			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);

			break;

		default:
@@ -5091,6 +5092,7 @@ static int gfx_v11_0_set_powergating_state(void *handle, 
		amdgpu_gfx_off_ctrl(adev, enable);

		break;

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 4):

		gfx_v11_cntl_pg(adev, enable);

		amdgpu_gfx_off_ctrl(adev, enable);

		break;
@@ -5114,6 +5116,7 @@ static int gfx_v11_0_set_clockgating_state(void *handle, 
	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 2):

	case IP_VERSION(11, 0, 3):

	case IP_VERSION(11, 0, 4):

	        gfx_v11_0_update_gfx_clock_gating(adev,

	                        state ==  AMD_CG_STATE_GATE);

	        break;