Loading drivers/pci/controller/vmd.c +17 −2 Original line number Diff line number Diff line Loading @@ -541,8 +541,23 @@ static void vmd_domain_reset(struct vmd_dev *vmd) PCI_CLASS_BRIDGE_PCI)) continue; memset_io(base + PCI_IO_BASE, 0, PCI_ROM_ADDRESS1 - PCI_IO_BASE); /* * Temporarily disable the I/O range before updating * PCI_IO_BASE. */ writel(0x0000ffff, base + PCI_IO_BASE_UPPER16); /* Update lower 16 bits of I/O base/limit */ writew(0x00f0, base + PCI_IO_BASE); /* Update upper 16 bits of I/O base/limit */ writel(0, base + PCI_IO_BASE_UPPER16); /* MMIO Base/Limit */ writel(0x0000fff0, base + PCI_MEMORY_BASE); /* Prefetchable MMIO Base/Limit */ writel(0, base + PCI_PREF_LIMIT_UPPER32); writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE); writel(0xffffffff, base + PCI_PREF_BASE_UPPER32); } } } Loading Loading
drivers/pci/controller/vmd.c +17 −2 Original line number Diff line number Diff line Loading @@ -541,8 +541,23 @@ static void vmd_domain_reset(struct vmd_dev *vmd) PCI_CLASS_BRIDGE_PCI)) continue; memset_io(base + PCI_IO_BASE, 0, PCI_ROM_ADDRESS1 - PCI_IO_BASE); /* * Temporarily disable the I/O range before updating * PCI_IO_BASE. */ writel(0x0000ffff, base + PCI_IO_BASE_UPPER16); /* Update lower 16 bits of I/O base/limit */ writew(0x00f0, base + PCI_IO_BASE); /* Update upper 16 bits of I/O base/limit */ writel(0, base + PCI_IO_BASE_UPPER16); /* MMIO Base/Limit */ writel(0x0000fff0, base + PCI_MEMORY_BASE); /* Prefetchable MMIO Base/Limit */ writel(0, base + PCI_PREF_LIMIT_UPPER32); writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE); writel(0xffffffff, base + PCI_PREF_BASE_UPPER32); } } } Loading