Commit 65844828 authored by Sandipan Das's avatar Sandipan Das Committed by Arnaldo Carvalho de Melo
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perf vendor events amd: Add Zen 4 core events 



Add core events taken from Section 2.1.15.4 "Core Performance Monitor
Counters" in the Processor Programming Reference (PPR) for AMD Family
19h Model 11h Revision B1 processors. This constitutes events which
capture op dispatch, execution and retirement, branch prediction, L1
and L2 cache activity, TLB activity, etc.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jirka Hladky <jhladky@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/20221214082652.419965-2-sandipan.das@amd.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6abaa020

tools/perf/pmu-events/arch/x86/amdzen4/branch.json

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[

  {

    "EventName": "bp_l2_btb_correct",

    "EventCode": "0x8b",

    "BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."

  },

  {

    "EventName": "bp_dyn_ind_pred",

    "EventCode": "0x8e",

    "BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."

  },

  {

    "EventName": "bp_de_redirect",

    "EventCode": "0x91",

    "BriefDescription": "Instruction decoder corrects the predicted target and resteers the branch predictor."

  },

  {

    "EventName": "ex_ret_brn",

    "EventCode": "0xc2",

    "BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."

  },

  {

    "EventName": "ex_ret_brn_misp",

    "EventCode": "0xc3",

    "BriefDescription": "Retired branch instructions mispredicted."

  },

  {

    "EventName": "ex_ret_brn_tkn",

    "EventCode": "0xc4",

    "BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."

  },

  {

    "EventName": "ex_ret_brn_tkn_misp",

    "EventCode": "0xc5",

    "BriefDescription": "Retired taken branch instructions mispredicted."

  },

  {

    "EventName": "ex_ret_brn_far",

    "EventCode": "0xc6",

    "BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."

  },

  {

    "EventName": "ex_ret_near_ret",

    "EventCode": "0xc8",

    "BriefDescription": "Retired near returns (RET or RET Iw)."

  },

  {

    "EventName": "ex_ret_near_ret_mispred",

    "EventCode": "0xc9",

    "BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."

  },

  {

    "EventName": "ex_ret_brn_ind_misp",

    "EventCode": "0xca",

    "BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."

  },

  {

    "EventName": "ex_ret_ind_brch_instr",

    "EventCode": "0xcc",

    "BriefDescription": "Retired indirect branch instructions."

  },

  {

    "EventName": "ex_ret_cond",

    "EventCode": "0xd1",

    "BriefDescription": "Retired conditional branch instructions."

  },

  {

    "EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",

    "EventCode": "0x1c7",

    "BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."

  },

  {

    "EventName": "ex_ret_uncond_brnch_instr_mispred",

    "EventCode": "0x1c8",

    "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."

  },

  {

    "EventName": "ex_ret_uncond_brnch_instr",

    "EventCode": "0x1c9",

    "BriefDescription": "Retired unconditional branch instructions."

  }

]

tools/perf/pmu-events/arch/x86/amdzen4/cache.json

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tools/perf/pmu-events/arch/x86/amdzen4/core.json

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[

  {

    "EventName": "ls_locks.bus_lock",

    "EventCode": "0x25",

    "BriefDescription": "Retired Lock instructions which caused a bus lock.",

    "UMask": "0x01"

  },

  {

    "EventName": "ls_ret_cl_flush",

    "EventCode": "0x26",

    "BriefDescription": "Retired CLFLUSH instructions."

  },

  {

    "EventName": "ls_ret_cpuid",

    "EventCode": "0x27",

    "BriefDescription": "Retired CPUID instructions."

  },

  {

    "EventName": "ls_smi_rx",

    "EventCode": "0x2b",

    "BriefDescription": "SMIs received."

  },

  {

    "EventName": "ls_int_taken",

    "EventCode": "0x2c",

    "BriefDescription": "Interrupts taken."

  },

  {

    "EventName": "ls_not_halted_cyc",

    "EventCode": "0x76",

    "BriefDescription": "Core cycles not in halt."

  },

  {

    "EventName": "ex_ret_instr",

    "EventCode": "0xc0",

    "BriefDescription": "Retired instructions."

  },

  {

    "EventName": "ex_ret_ops",

    "EventCode": "0xc1",

    "BriefDescription": "Retired macro-ops."

  },

  {

    "EventName": "ex_div_busy",

    "EventCode": "0xd3",

    "BriefDescription": "Number of cycles the divider is busy."

  },

  {

    "EventName": "ex_div_count",

    "EventCode": "0xd4",

    "BriefDescription": "Divide ops executed."

  },

  {

    "EventName": "ex_no_retire.empty",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",

    "UMask": "0x01"

  },

  {

    "EventName": "ex_no_retire.not_complete",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",

    "UMask": "0x02"

  },

  {

    "EventName": "ex_no_retire.other",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",

    "UMask": "0x08"

  },

  {

    "EventName": "ex_no_retire.thread_not_selected",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",

    "UMask": "0x10"

  },

  {

    "EventName": "ex_no_retire.load_not_complete",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",

    "UMask": "0xa2"

  },

  {

    "EventName": "ex_no_retire.all",

    "EventCode": "0xd6",

    "BriefDescription": "Cycles with no retire for any reason.",

    "UMask": "0x1b"

  },

  {

    "EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",

    "EventCode": "0x120",

    "BriefDescription": "Reference cycles (P0 frequency) not in halt .",

    "UMask": "0x1"

  },

  {

    "EventName": "ex_ret_ucode_instr",

    "EventCode": "0x1c1",

    "BriefDescription": "Retired microcoded instructions."

  },

  {

    "EventName": "ex_ret_ucode_ops",

    "EventCode": "0x1c2",

    "BriefDescription": "Retired microcode ops."

  },

  {

    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",

    "EventCode": "0x1cf",

    "BriefDescription": "Ops tagged by IBS.",

    "UMask": "0x01"

  },

  {

    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",

    "EventCode": "0x1cf",

    "BriefDescription": "Ops tagged by IBS that retired.",

    "UMask": "0x02"

  },

  {

    "EventName": "ex_ret_fused_instr",

    "EventCode": "0x1d0",

    "BriefDescription": "Retired fused instructions."

  }

]

tools/perf/pmu-events/arch/x86/amdzen4/floating-point.json

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tools/perf/pmu-events/arch/x86/amdzen4/memory.json

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[

  {

    "EventName": "ls_bad_status2.stli_other",

    "EventCode": "0x24",

    "BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",

    "UMask": "0x02"

  },

  {

    "EventName": "ls_dispatch.ld_dispatch",

    "EventCode": "0x29",

    "BriefDescription": "Number of memory load operations dispatched to the load-store unit.",

    "UMask": "0x01"

  },

  {

    "EventName": "ls_dispatch.store_dispatch",

    "EventCode": "0x29",

    "BriefDescription": "Number of memory store operations dispatched to the load-store unit.",

    "UMask": "0x02"

  },

  {

    "EventName": "ls_dispatch.ld_st_dispatch",

    "EventCode": "0x29",

    "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",

    "UMask": "0x04"

  },

  {

    "EventName": "ls_stlf",

    "EventCode": "0x35",

    "BriefDescription": "Store-to-load-forward (STLF) hits."

  },

  {

    "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",

    "EventCode": "0x37",

    "BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",

    "UMask": "0x01"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",

    "UMask": "0x01"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",

    "UMask": "0x02"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",

    "UMask": "0x04"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",

    "UMask": "0x08"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",

    "UMask": "0x10"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",

    "UMask": "0x20"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",

    "UMask": "0x40"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",

    "UMask": "0x80"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.all_l2_miss",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",

    "UMask": "0xf0"

  },

  {

    "EventName": "ls_l1_d_tlb_miss.all",

    "EventCode": "0x45",

    "BriefDescription": "L1 DTLB misses for all page sizes.",

    "UMask": "0xff"

  },

  {

    "EventName": "ls_misal_loads.ma64",

    "EventCode": "0x47",

    "BriefDescription": "64B misaligned (cacheline crossing) loads.",

    "UMask": "0x01"

  },

  {

    "EventName": "ls_misal_loads.ma4k",

    "EventCode": "0x47",

    "BriefDescription": "4kB misaligned (page crossing) loads.",

    "UMask": "0x02"

  },

  {

    "EventName": "ls_tlb_flush.all",

    "EventCode": "0x78",

    "BriefDescription": "All TLB Flushes.",

    "UMask": "0xff"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_hit",

    "EventCode": "0x84",

    "BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",

    "UMask": "0x01"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",

    "UMask": "0x02"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",

    "UMask": "0x04"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",

    "UMask": "0x08"

  },

  {

    "EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",

    "EventCode": "0x85",

    "BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",

    "UMask": "0x0f"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.if4k",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",

    "UMask": "0x01"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.if2m",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",

    "UMask": "0x02"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.if1g",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",

    "UMask": "0x04"

  },

  {

    "EventName": "bp_l1_tlb_fetch_hit.all",

    "EventCode": "0x94",

    "BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",

    "UMask": "0x07"

  }

]