Commit 651a8536 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:

 - Tag Intel pin control as supported in MAINTAINERS

 - Fix a NULL pointer exception in the Aspeed driver

 - Correct some NAND functions in the Sunxi A83T driver

 - Use the right offset for some Sunxi pins

 - Fix a zero base offset in the Freescale (NXP) i.MX93

 - Fix the IRQ support in the STM32 driver

* tag 'pinctrl-v5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: stm32: fix optional IRQ support to gpios
  pinctrl: imx: Add the zero base flag for imx93
  pinctrl: sunxi: sunxi_pconf_set: use correct offset
  pinctrl: sunxi: a83t: Fix NAND function name for some pins
  pinctrl: aspeed: Fix potential NULL dereference in aspeed_pinmux_set_mux()
  MAINTAINERS: Update Intel pin control to Supported
parents a382f8fe a1d4ef1a

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -15792,7 +15792,7 @@ F: drivers/pinctrl/freescale/ 
PIN CONTROLLER - INTEL

M:	Mika Westerberg <mika.westerberg@linux.intel.com>

M:	Andy Shevchenko <andy@kernel.org>

S:	Maintained

S:	Supported

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git

F:	drivers/pinctrl/intel/
































drivers/pinctrl/aspeed/pinctrl-aspeed.c



+2
−2






























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@@ -236,11 +236,11 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,







		const struct aspeed_sig_expr **funcs;









		const struct aspeed_sig_expr ***prios;



















		pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);



















		if (!pdesc)









			return -EINVAL;



















		pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);



















		prios = pdesc->prios;



















		if (!prios)
































drivers/pinctrl/freescale/pinctrl-imx93.c



+1
−0






























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Diff line







@@ -239,6 +239,7 @@ static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = {







static const struct imx_pinctrl_soc_info imx93_pinctrl_info = {









	.pins = imx93_pinctrl_pads,









	.npins = ARRAY_SIZE(imx93_pinctrl_pads),









	.flags = ZERO_OFFSET_VALID,









	.gpr_compatible = "fsl,imx93-iomuxc-gpr",









};










































drivers/pinctrl/stm32/pinctrl-stm32.c



+12
−8






























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Diff line







@@ -1338,17 +1338,19 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode







	bank->secure_control = pctl->match_data->secure_control;









	spin_lock_init(&bank->lock);



















	if (pctl->domain) {









		/* create irq hierarchical domain */









		bank->fwnode = fwnode;



















	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,









					STM32_GPIO_IRQ_LINE, bank->fwnode,









					&stm32_gpio_domain_ops, bank);









		bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,









							   bank->fwnode, &stm32_gpio_domain_ops,









							   bank);



















		if (!bank->domain) {









			err = -ENODEV;









			goto err_clk;









		}









	}



















	err = gpiochip_add_data(&bank->gpio_chip, bank);









	if (err) {








@@ -1510,6 +1512,8 @@ int stm32_pctl_probe(struct platform_device *pdev)







	pctl->domain = stm32_pctrl_get_irq_domain(pdev);









	if (IS_ERR(pctl->domain))









		return PTR_ERR(pctl->domain);









	if (!pctl->domain)









		dev_warn(dev, "pinctrl without interrupt support\n");



















	/* hwspinlock is optional */









	hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
































drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c



+5
−5






























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Diff line







@@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = {







	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),









		  SUNXI_FUNCTION(0x0, "gpio_in"),









		  SUNXI_FUNCTION(0x1, "gpio_out"),









		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */









		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ6 */









		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */









	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),









		  SUNXI_FUNCTION(0x0, "gpio_in"),









		  SUNXI_FUNCTION(0x1, "gpio_out"),









		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */









		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ7 */









		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */









	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),









		  SUNXI_FUNCTION(0x0, "gpio_in"),









		  SUNXI_FUNCTION(0x1, "gpio_out"),









		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */









		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQS */









		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */









	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),









		  SUNXI_FUNCTION(0x0, "gpio_in"),









		  SUNXI_FUNCTION(0x1, "gpio_out"),









		  SUNXI_FUNCTION(0x2, "nand")),		/* CE2 */









		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE2 */









	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),









		  SUNXI_FUNCTION(0x0, "gpio_in"),









		  SUNXI_FUNCTION(0x1, "gpio_out"),









		  SUNXI_FUNCTION(0x2, "nand")),		/* CE3 */









		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE3 */









	/* Hole */









	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),









		  SUNXI_FUNCTION(0x0, "gpio_in"),