Commit 649179e5 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-fixes-for-v6.1-tag1' of... 

Merge tag 'renesas-clk-fixes-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-fixes

Pull Renesas clk driver fixes from Geert Uytterhoeven:

 - Correct the parent clocks for the High Speed Serial Communication
   Interfaces with FIFO (HSCIF) modules on the R-Car V4H SoC.

   Note that HSCIF0 is used for the serial console on the White-Hawk
   development board.

* tag 'renesas-clk-fixes-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779g0: Fix HSCIF parent clocks
  clk: renesas: r8a779g0: Add SASYNCPER clocks
parents 8fbf8636 a9003f74

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+9 −4
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ enum clk_ids { 
	CLK_S0_VIO,

	CLK_S0_VC,

	CLK_S0_HSC,

	CLK_SASYNCPER,

	CLK_SV_VIP,

	CLK_SV_IR,

	CLK_SDSRC,
@@ -84,6 +85,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED(".s0_vio",	CLK_S0_VIO,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".s0_vc",	CLK_S0_VC,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".s0_hsc",	CLK_S0_HSC,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".sasyncper",	CLK_SASYNCPER,	CLK_PLL5_DIV4,	3, 1),

	DEF_FIXED(".sv_vip",	CLK_SV_VIP,	CLK_PLL1,	5, 1),

	DEF_FIXED(".sv_ir",	CLK_SV_IR,	CLK_PLL1,	5, 1),

	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
@@ -128,6 +130,9 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("s0d4_hsc",	R8A779G0_CLK_S0D4_HSC,	CLK_S0_HSC,	4, 1),

	DEF_FIXED("cl16m_hsc",	R8A779G0_CLK_CL16M_HSC,	CLK_S0_HSC,	48, 1),

	DEF_FIXED("s0d2_cc",	R8A779G0_CLK_S0D2_CC,	CLK_S0,		2, 1),

	DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),

	DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),

	DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),

	DEF_FIXED("svd1_ir",	R8A779G0_CLK_SVD1_IR,	CLK_SV_IR,	1, 1),

	DEF_FIXED("svd2_ir",	R8A779G0_CLK_SVD2_IR,	CLK_SV_IR,	2, 1),

	DEF_FIXED("svd1_vip",	R8A779G0_CLK_SVD1_VIP,	CLK_SV_VIP,	1, 1),
@@ -153,10 +158,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif3",	517,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif3",	517,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("i2c0",		518,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c1",		519,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779G0_CLK_S0D6_PER),