Commit a9003f74 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a779g0: Fix HSCIF parent clocks 



As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.

Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car V4H Hardware User's Manual rev. 0.54.

Fixes: 0ab55cf1 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/b7928abc8b9f53d5b06ec8624342f449de3d24ec.1665147497.git.geert+renesas@glider.be
parent ba5284eb

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+4 −4
Original line number Diff line number Diff line
@@ -158,10 +158,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif3",	517,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif3",	517,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("i2c0",		518,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c1",		519,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779G0_CLK_S0D6_PER),