Commit 63186094 authored by Maciej Wieczor-Retman's avatar Maciej Wieczor-Retman Committed by Xiaochen Shen
Browse files

x86/resctrl: Enable non-contiguous CBMs in Intel CAT 

mainline inclusion
from mainline-v6.7-rc1
commit 0e3cd31f6e9074886dea5a999bfcc563d144e7de
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8WO9B
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0e3cd31f6e9074886dea5a999bfcc563d144e7de



--------------------------------

The setting for non-contiguous 1s support in Intel CAT is
hardcoded to false. On these systems, writing non-contiguous
1s into the schemata file will fail before resctrl passes
the value to the hardware.

In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped
being reserved and now carry information about non-contiguous 1s
value support for L3 and L2 cache respectively. The CAT
capacity bitmask (CBM) supports a non-contiguous 1s value if
the bit is set.

The exception are Haswell systems where non-contiguous 1s value
support needs to stay disabled since they can't make use of CPUID
for Cache allocation.

Intel-SIG: commit 0e3cd31f6e90 x86/resctrl: Enable non-contiguous CBMs in Intel CAT.
Incremental backporting patches for Intel RDT on Intel Xeon platform.

Originally-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Signed-off-by: default avatarMaciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: default avatarPeter Newman <peternewman@google.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Tested-by: default avatarPeter Newman <peternewman@google.com>
Link: https://lore.kernel.org/r/1849b487256fe4de40b30f88450cba3d9abc9171.1696934091.git.maciej.wieczor-retman@intel.com


Signed-off-by: default avatarXiaochen Shen <xiaochen.shen@intel.com>
parent 03a649b3

arch/x86/kernel/cpu/resctrl/core.c

+6 −3
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void) 
	r->cache.cbm_len = 20;

	r->cache.shareable_bits = 0xc0000;

	r->cache.min_cbm_bits = 2;

	r->cache.arch_has_sparse_bitmasks = false;

	r->alloc_capable = true;



	rdt_alloc_capable = true;
@@ -267,15 +268,18 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 
{

	struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r);

	union cpuid_0x10_1_eax eax;

	union cpuid_0x10_x_ecx ecx;

	union cpuid_0x10_x_edx edx;

	u32 ebx, ecx;

	u32 ebx;



	cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);

	cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full);

	hw_res->num_closid = edx.split.cos_max + 1;

	r->cache.cbm_len = eax.split.cbm_len + 1;

	r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1;

	r->cache.shareable_bits = ebx & r->default_ctrl;

	r->data_width = (r->cache.cbm_len + 3) / 4;

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)

		r->cache.arch_has_sparse_bitmasks = ecx.split.noncont;

	r->alloc_capable = true;

}
@@ -872,7 +876,6 @@ static __init void rdt_init_res_defs_intel(void) 


		if (r->rid == RDT_RESOURCE_L3 ||

		    r->rid == RDT_RESOURCE_L2) {

			r->cache.arch_has_sparse_bitmasks = false;

			r->cache.arch_has_per_cpu_cfg = false;

			r->cache.min_cbm_bits = 1;

		} else if (r->rid == RDT_RESOURCE_MBA) {

arch/x86/kernel/cpu/resctrl/ctrlmondata.c

+6 −4
Original line number Diff line number Diff line
@@ -87,10 +87,12 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s, 


/*

 * Check whether a cache bit mask is valid.

 * For Intel the SDM says:

 *	Please note that all (and only) contiguous '1' combinations

 *	are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).

 * Additionally Haswell requires at least two bits set.

 * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID:

 *   - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1

 *   - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1

 *

 * Haswell does not support a non-contiguous 1s value and additionally

 * requires at least two bits set.

 * AMD allows non-contiguous bitmasks.

 */

static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)

arch/x86/kernel/cpu/resctrl/internal.h

+9 −0
Original line number Diff line number Diff line
@@ -492,6 +492,15 @@ union cpuid_0x10_3_eax { 
	unsigned int full;

};



/* CPUID.(EAX=10H, ECX=ResID).ECX */

union cpuid_0x10_x_ecx {

	struct {

		unsigned int reserved:3;

		unsigned int noncont:1;

	} split;

	unsigned int full;

};



/* CPUID.(EAX=10H, ECX=ResID).EDX */

union cpuid_0x10_x_edx {

	struct {