x86/resctrl: Enable non-contiguous CBMs in Intel CAT

mainline inclusion
from mainline-v6.7-rc1
commit 0e3cd31f6e9074886dea5a999bfcc563d144e7de
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8WO9B
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0e3cd31f6e9074886dea5a999bfcc563d144e7de



--------------------------------

The setting for non-contiguous 1s support in Intel CAT is
hardcoded to false. On these systems, writing non-contiguous
1s into the schemata file will fail before resctrl passes
the value to the hardware.

In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped
being reserved and now carry information about non-contiguous 1s
value support for L3 and L2 cache respectively. The CAT
capacity bitmask (CBM) supports a non-contiguous 1s value if
the bit is set.

The exception are Haswell systems where non-contiguous 1s value
support needs to stay disabled since they can't make use of CPUID
for Cache allocation.

Intel-SIG: commit 0e3cd31f6e90 x86/resctrl: Enable non-contiguous CBMs in Intel CAT.
Incremental backporting patches for Intel RDT on Intel Xeon platform.

Originally-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Peter Newman <peternewman@google.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Peter Newman <peternewman@google.com>
Link: https://lore.kernel.org/r/1849b487256fe4de40b30f88450cba3d9abc9171.1696934091.git.maciej.wieczor-retman@intel.com


Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>