Commit 03a649b3 authored Oct 10, 2023 by Maciej Wieczor-Retman Committed by Xiaochen Shen Jan 16, 2024

x86/resctrl: Rename arch_has_sparse_bitmaps

mainline inclusion
from mainline-v6.7-rc1
commit 39c6eed1f61594f737160e498d29673edbd9eefd
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8WO9B
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=39c6eed1f61594f737160e498d29673edbd9eefd



--------------------------------

Rename arch_has_sparse_bitmaps to arch_has_sparse_bitmasks to ensure
consistent terminology throughout resctrl.

Intel-SIG: commit 39c6eed1f615 x86/resctrl: Rename arch_has_sparse_bitmaps.
Incremental backporting patches for Intel RDT on Intel Xeon platform.

Suggested-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Peter Newman <peternewman@google.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Peter Newman <peternewman@google.com>
Link: https://lore.kernel.org/r/e330fcdae873ef1a831e707025a4b70fa346666e.1696934091.git.maciej.wieczor-retman@intel.com


Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>

parent aefe6d3e

arch/x86/kernel/cpu/resctrl/core.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -872,7 +872,7 @@ static __init void rdt_init_res_defs_intel(void)

		if (r->rid == RDT_RESOURCE_L3 \|\|
		r->rid == RDT_RESOURCE_L2) {
		r->cache.arch_has_sparse_bitmaps = false;
		r->cache.arch_has_sparse_bitmasks = false;
		r->cache.arch_has_per_cpu_cfg = false;
		r->cache.min_cbm_bits = 1;
		} else if (r->rid == RDT_RESOURCE_MBA) {
		@@ -892,7 +892,7 @@ static __init void rdt_init_res_defs_amd(void)

		if (r->rid == RDT_RESOURCE_L3 \|\|
		r->rid == RDT_RESOURCE_L2) {
		r->cache.arch_has_sparse_bitmaps = true;
		r->cache.arch_has_sparse_bitmasks = true;
		r->cache.arch_has_per_cpu_cfg = true;
		r->cache.min_cbm_bits = 0;
		} else if (r->rid == RDT_RESOURCE_MBA) {

arch/x86/kernel/cpu/resctrl/ctrlmondata.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -113,8 +113,8 @@ static bool cbm_validate(char buf, u32 data, struct rdt_resource *r)
		first_bit = find_first_bit(&val, cbm_len);
		zero_bit = find_next_zero_bit(&val, cbm_len, first_bit);

		/* Are non-contiguous bitmaps allowed? */
		if (!r->cache.arch_has_sparse_bitmaps &&
		/* Are non-contiguous bitmasks allowed? */
		if (!r->cache.arch_has_sparse_bitmasks &&
		(find_next_bit(&val, cbm_len, zero_bit) < cbm_len)) {
		rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val);
		return false;

include/linux/resctrl.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -94,7 +94,7 @@ struct rdt_domain {
		* zero CBM.
		* @shareable_bits: Bitmask of shareable resource with other
		* executing entities
		* @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid.
		* @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid.
		* @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache
		* level has CPU scope.
		*/
		@@ -102,7 +102,7 @@ struct resctrl_cache {
		unsigned int cbm_len;
		unsigned int min_cbm_bits;
		unsigned int shareable_bits;
		bool arch_has_sparse_bitmaps;
		bool arch_has_sparse_bitmasks;
		bool arch_has_per_cpu_cfg;
		};