Unverified Commit 618d1293 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v6.5-rockchip-drivers1' of... 

Merge tag 'v6.5-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/drivers

An addition to the rk3588 power-domains, some new syscon compatibles for
rk3588-based "General-register-files" register areas and a move to
C99 array inits for the dtpm driver to fix sparse warnings.

* tag 'v6.5-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: dtpm: use C99 array init syntax
  dt-bindings: soc: rockchip: add rk3588 pipe-phy syscon
  dt-bindings: soc: rockchip: add rk3588 usb2phy syscon
  soc: rockchip: power-domain: add rk3588 mem module support

Link: https://lore.kernel.org/r/10286366.nUPlyArG6x@phil


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 3a00b1c4 a10b3841

Documentation/devicetree/bindings/soc/rockchip/grf.yaml

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ properties: 
              - rockchip,rk3588-bigcore1-grf

              - rockchip,rk3588-ioc

              - rockchip,rk3588-php-grf

              - rockchip,rk3588-pipe-phy-grf

              - rockchip,rk3588-sys-grf

              - rockchip,rk3588-pcie3-phy-grf

              - rockchip,rk3588-pcie3-pipe-grf
@@ -52,6 +53,7 @@ properties: 
              - rockchip,rk3399-pmugrf

              - rockchip,rk3568-grf

              - rockchip,rk3568-pmugrf

              - rockchip,rk3588-usb2phy-grf

              - rockchip,rv1108-grf

              - rockchip,rv1108-pmugrf

              - rockchip,rv1126-grf
@@ -199,6 +201,7 @@ allOf: 
              - rockchip,rk3308-usb2phy-grf

              - rockchip,rk3328-usb2phy-grf

              - rockchip,rk3399-grf

              - rockchip,rk3588-usb2phy-grf

              - rockchip,rv1108-grf



    then:

drivers/soc/rockchip/dtpm.c

+27 −27
Original line number Diff line number Diff line
@@ -12,33 +12,33 @@ 
#include <linux/platform_device.h>



static struct dtpm_node __initdata rk3399_hierarchy[] = {

	[0]{ .name = "rk3399",

	[0] = { .name = "rk3399",

		.type = DTPM_NODE_VIRTUAL },

	[1]{ .name = "package",

	[1] = { .name = "package",

		.type = DTPM_NODE_VIRTUAL,

		.parent = &rk3399_hierarchy[0] },

	[2]{ .name = "/cpus/cpu@0",

	[2] = { .name = "/cpus/cpu@0",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[3]{ .name = "/cpus/cpu@1",

	[3] = { .name = "/cpus/cpu@1",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[4]{ .name = "/cpus/cpu@2",

	[4] = { .name = "/cpus/cpu@2",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[5]{ .name = "/cpus/cpu@3",

	[5] = { .name = "/cpus/cpu@3",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[6]{ .name = "/cpus/cpu@100",

	[6] = { .name = "/cpus/cpu@100",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[7]{ .name = "/cpus/cpu@101",

	[7] = { .name = "/cpus/cpu@101",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[8]{ .name = "/gpu@ff9a0000",

	[8] = { .name = "/gpu@ff9a0000",

		.type = DTPM_NODE_DT,

		.parent = &rk3399_hierarchy[1] },

	[9]{ /* sentinel */ }

	[9] = { /* sentinel */ }

};



static struct of_device_id __initdata rockchip_dtpm_match_table[] = {

drivers/soc/rockchip/pm_domains.c

+125 −35
Original line number Diff line number Diff line
@@ -43,8 +43,10 @@ struct rockchip_domain_info { 
	bool active_wakeup;

	int pwr_w_mask;

	int req_w_mask;

	int mem_status_mask;

	int repair_status_mask;

	u32 pwr_offset;

	u32 mem_offset;

	u32 req_offset;

};
@@ -54,6 +56,9 @@ struct rockchip_pmu_info { 
	u32 req_offset;

	u32 idle_offset;

	u32 ack_offset;

	u32 mem_pwr_offset;

	u32 chain_status_offset;

	u32 mem_status_offset;

	u32 repair_status_offset;



	u32 core_pwrcnt_offset;
@@ -119,13 +124,15 @@ struct rockchip_pmu { 
	.active_wakeup = wakeup,			\

}



#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup)	\

#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup)	\

{							\

	.name = _name,					\

	.pwr_offset = p_offset,				\

	.pwr_w_mask = (pwr) << 16,			\

	.pwr_mask = (pwr),				\

	.status_mask = (status),			\

	.mem_offset = m_offset,				\

	.mem_status_mask = (m_status),			\

	.repair_status_mask = (r_status),		\

	.req_offset = r_offset,				\

	.req_w_mask = (req) << 16,			\
@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void) 
}

EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);



#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup)	\

	DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)

#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)	\

	DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)



static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)

{
@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) 
	return !(val & pd->info->status_mask);

}



static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)

{

	struct rockchip_pmu *pmu = pd->pmu;

	unsigned int val;



	regmap_read(pmu->regmap,

		    pmu->info->mem_status_offset + pd->info->mem_offset, &val);



	/* 1'b0: power on, 1'b1: power off */

	return !(val & pd->info->mem_status_mask);

}



static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)

{

	struct rockchip_pmu *pmu = pd->pmu;

	unsigned int val;



	regmap_read(pmu->regmap,

		    pmu->info->chain_status_offset + pd->info->mem_offset, &val);



	/* 1'b1: power on, 1'b0: power off */

	return val & pd->info->mem_status_mask;

}



static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)

{

	struct rockchip_pmu *pmu = pd->pmu;

	struct generic_pm_domain *genpd = &pd->genpd;

	bool is_on;

	int ret = 0;



	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,

					is_on == true, 0, 10000);

	if (ret) {

		dev_err(pmu->dev,

			"failed to get chain status '%s', target_on=1, val=%d\n",

			genpd->name, is_on);

		goto error;

	}



	udelay(20);



	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,

		     (pd->info->pwr_mask | pd->info->pwr_w_mask));

	wmb();



	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,

					is_on == false, 0, 10000);

	if (ret) {

		dev_err(pmu->dev,

			"failed to get mem status '%s', target_on=0, val=%d\n",

			genpd->name, is_on);

		goto error;

	}



	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,

		     pd->info->pwr_w_mask);

	wmb();



	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,

					is_on == true, 0, 10000);

	if (ret) {

		dev_err(pmu->dev,

			"failed to get mem status '%s', target_on=1, val=%d\n",

			genpd->name, is_on);

	}



error:

	return ret;

}



static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,

					     bool on)

{

	struct rockchip_pmu *pmu = pd->pmu;

	struct generic_pm_domain *genpd = &pd->genpd;

	u32 pd_pwr_offset = pd->info->pwr_offset;

	bool is_on;

	bool is_on, is_mem_on = false;



	if (pd->info->pwr_mask == 0)

		return;

	else if (pd->info->pwr_w_mask)



	if (on && pd->info->mem_status_mask)

		is_mem_on = rockchip_pmu_domain_is_mem_on(pd);



	if (pd->info->pwr_w_mask)

		regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,

			     on ? pd->info->pwr_w_mask :

			     (pd->info->pwr_mask | pd->info->pwr_w_mask));
@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, 


	wmb();



	if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))

		return;



	if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,

				      is_on == on, 0, 10000)) {

		dev_err(pmu->dev,
@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, 
	pd->genpd.flags = GENPD_FLAG_PM_CLK;

	if (pd_info->active_wakeup)

		pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;

	pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));

	pm_genpd_init(&pd->genpd, NULL,

		      !rockchip_pmu_domain_is_on(pd) ||

		      (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));



	pmu->genpd_data.domains[id] = &pd->genpd;

	return 0;
@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = { 
};



static const struct rockchip_domain_info rk3588_pm_domains[] = {

	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),

	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0,       0x0, 0,       0,       false),

	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0,       0x0, 0,       0,       false),

	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       BIT(2),  0x0, BIT(1),  BIT(1),  false),

	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       BIT(3),  0x0, BIT(2),  BIT(2),  false),

	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       BIT(4),  0x0, BIT(3),  BIT(3),  false),

	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       BIT(5),  0x0, BIT(4),  BIT(4),  false),

	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       BIT(6),  0x0, BIT(5),  BIT(5),  false),

	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       BIT(7),  0x0, BIT(6),  BIT(6),  false),

	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       BIT(8),  0x0, BIT(7),  BIT(7),  false),

	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       BIT(9),  0x0, BIT(8),  BIT(8),  false),

	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       BIT(10), 0x0, 0,       0,       false),

	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       BIT(11), 0x0, BIT(9),  BIT(9),  false),

	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       BIT(12), 0x0, BIT(10), BIT(10), false),

	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       BIT(13), 0x0, 0,       0,       false),

	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       BIT(14), 0x0, BIT(11), BIT(11), false),

	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       BIT(15), 0x0, BIT(12), BIT(12), false),

	[RK3588_PD_VOP]		= DOMAIN_RK3588("vop",     0x4, BIT(1),  0,       BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),

	[RK3588_PD_VO0]		= DOMAIN_RK3588("vo0",     0x4, BIT(2),  0,       BIT(17), 0x0, BIT(15), BIT(15), false),

	[RK3588_PD_VO1]		= DOMAIN_RK3588("vo1",     0x4, BIT(3),  0,       BIT(18), 0x4, BIT(0),  BIT(16), false),

	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       BIT(19), 0x4, BIT(1),  BIT(17), false),

	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       BIT(20), 0x4, BIT(5),  BIT(21), false),

	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       BIT(21), 0x0, 0,       0,       false),

	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       BIT(22), 0x0, 0,       0,       true),

	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0,       0x4, BIT(2),  BIT(18), false),

	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       BIT(23), 0x0, 0,       0,       false),

	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       BIT(24), 0x4, BIT(3),  BIT(19), false),

	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       BIT(25), 0x4, BIT(4),  BIT(20), true),

	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       BIT(26), 0x0, 0,       0,       false),

	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       0x0, 0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),

	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0x0, 0,       0,       0x0, 0,       0,       false),

	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0x0, 0,       0,       0x0, 0,       0,       false),

	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       0x0, BIT(11), BIT(2),  0x0, BIT(1),  BIT(1),  false),

	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       0x0, BIT(12), BIT(3),  0x0, BIT(2),  BIT(2),  false),

	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       0x0, BIT(13), BIT(4),  0x0, BIT(3),  BIT(3),  false),

	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       0x0, BIT(14), BIT(5),  0x0, BIT(4),  BIT(4),  false),

	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       0x0, BIT(15), BIT(6),  0x0, BIT(5),  BIT(5),  false),

	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       0x0, BIT(16), BIT(7),  0x0, BIT(6),  BIT(6),  false),

	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       0x0, BIT(17), BIT(8),  0x0, BIT(7),  BIT(7),  false),

	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       0x0, BIT(18), BIT(9),  0x0, BIT(8),  BIT(8),  false),

	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       0x0, BIT(19), BIT(10), 0x0, 0,       0,       false),

	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       0x0, BIT(20), BIT(11), 0x0, BIT(9),  BIT(9),  false),

	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),

	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       0x0, BIT(22), BIT(13), 0x0, 0,       0,       false),

	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),

	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),

	[RK3588_PD_VOP]		= DOMAIN_RK3588("vop",     0x4, BIT(1),  0,       0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),

	[RK3588_PD_VO0]		= DOMAIN_RK3588("vo0",     0x4, BIT(2),  0,       0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),

	[RK3588_PD_VO1]		= DOMAIN_RK3588("vo1",     0x4, BIT(3),  0,       0x0, BIT(27), BIT(18), 0x4, BIT(0),  BIT(16), false),

	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       0x0, BIT(28), BIT(19), 0x4, BIT(1),  BIT(17), false),

	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       0x0, BIT(29), BIT(20), 0x4, BIT(5),  BIT(21), false),

	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       0x0, BIT(30), BIT(21), 0x0, 0,       0,       false),

	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       0x0, BIT(31), BIT(22), 0x0, 0,       0,       true),

	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0x4, 0,       0,       0x4, BIT(2),  BIT(18), false),

	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       0x4, BIT(1),  BIT(23), 0x0, 0,       0,       false),

	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       0x4, BIT(2),  BIT(24), 0x4, BIT(3),  BIT(19), false),

	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       0x4, BIT(3),  BIT(25), 0x4, BIT(4),  BIT(20), true),

	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       0x4, BIT(5),  BIT(26), 0x0, 0,       0,       false),

};



static const struct rockchip_pmu_info px30_pmu = {
@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk3588_pmu = { 
	.req_offset = 0x10c,

	.idle_offset = 0x120,

	.ack_offset = 0x118,

	.mem_pwr_offset = 0x1a0,

	.chain_status_offset = 0x1f0,

	.mem_status_offset = 0x1f8,

	.repair_status_offset = 0x290,



	.num_domains = ARRAY_SIZE(rk3588_pm_domains),