Commit 61279073 authored by Kenneth Feng's avatar Kenneth Feng Committed by Alex Deucher
Browse files

amd/powerplay: implement the vega12_force_clock_level interface 



pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force
gfxclk/uclk dpm level for Vega12

Signed-off-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 08ebb6e9

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

+41 −1
Original line number Diff line number Diff line
@@ -991,14 +991,54 @@ static uint32_t vega12_find_highest_dpm_level( 


static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)

{

	struct vega12_hwmgr *data = hwmgr->backend;

	if (data->smc_state_table.gfx_boot_level !=

			data->dpm_table.gfx_table.dpm_state.soft_min_level) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetSoftMinByFreq,

			PPCLK_GFXCLK<<16 | data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value);

		data->dpm_table.gfx_table.dpm_state.soft_min_level =

				data->smc_state_table.gfx_boot_level;

	}



	if (data->smc_state_table.mem_boot_level !=

			data->dpm_table.mem_table.dpm_state.soft_min_level) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetSoftMinByFreq,

			PPCLK_UCLK<<16 | data->dpm_table.mem_table.dpm_levels[data->smc_state_table.mem_boot_level].value);

		data->dpm_table.mem_table.dpm_state.soft_min_level =

				data->smc_state_table.mem_boot_level;

	}



	return 0;



}



static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)

{

	return 0;

	struct vega12_hwmgr *data = hwmgr->backend;

	if (data->smc_state_table.gfx_max_level !=

		data->dpm_table.gfx_table.dpm_state.soft_max_level) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetSoftMaxByFreq,

			/* plus the vale by 1 to align the resolution */

			PPCLK_GFXCLK<<16 | (data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_max_level].value + 1));

		data->dpm_table.gfx_table.dpm_state.soft_max_level =

				data->smc_state_table.gfx_max_level;

	}



	if (data->smc_state_table.mem_max_level !=

		data->dpm_table.mem_table.dpm_state.soft_max_level) {

		smum_send_msg_to_smc_with_parameter(hwmgr,

			PPSMC_MSG_SetSoftMaxByFreq,

			/* plus the vale by 1 to align the resolution */

			PPCLK_UCLK<<16 | (data->dpm_table.mem_table.dpm_levels[data->smc_state_table.mem_max_level].value + 1));

		data->dpm_table.mem_table.dpm_state.soft_max_level =

				data->smc_state_table.mem_max_level;

	}



	return 0;

}



int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)

{