Commit 08ebb6e9 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: Add APU support in vi_set_vce_clocks 



1. fix set vce clocks failed on Cz/St
   which lead 1s delay when boot up.
2. remove the workaround in vce_v3_0.c

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarShirish S <shirish.s@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 819a23f8

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -467,7 +467,7 @@ static int vce_v3_0_hw_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;





	vce_v3_0_override_vce_clock_gating(adev, true);

	vce_v3_0_override_vce_clock_gating(adev, true);

	if (!(adev->flags & AMD_IS_APU))



	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);

	amdgpu_asic_set_vce_clocks(adev, 10000, 10000);





	for (i = 0; i < adev->vce.num_rings; i++)

	for (i = 0; i < adev->vce.num_rings; i++)

drivers/gpu/drm/amd/amdgpu/vi.c

+25 −6
Original line number Original line Diff line number Diff line
@@ -757,6 +757,8 @@ static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 
#define ixGNB_CLK1_STATUS   0xD822010C

#define ixGNB_CLK1_STATUS   0xD822010C

#define ixGNB_CLK2_DFS_CNTL 0xD8220110

#define ixGNB_CLK2_DFS_CNTL 0xD8220110

#define ixGNB_CLK2_STATUS   0xD822012C

#define ixGNB_CLK2_STATUS   0xD822012C

#define ixGNB_CLK3_DFS_CNTL 0xD8220130

#define ixGNB_CLK3_STATUS   0xD822014C





static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

{

{
@@ -788,6 +790,22 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 
	int r, i;

	int r, i;

	struct atom_clock_dividers dividers;

	struct atom_clock_dividers dividers;

	u32 tmp;

	u32 tmp;

	u32 reg_ctrl;

	u32 reg_status;

	u32 status_mask;

	u32 reg_mask;



	if (adev->flags & AMD_IS_APU) {

		reg_ctrl = ixGNB_CLK3_DFS_CNTL;

		reg_status = ixGNB_CLK3_STATUS;

		status_mask = 0x00010000;

		reg_mask = CG_ECLK_CNTL__ECLK_DIVIDER_MASK;

	} else {

		reg_ctrl = ixCG_ECLK_CNTL;

		reg_status = ixCG_ECLK_STATUS;

		status_mask = CG_ECLK_STATUS__ECLK_STATUS_MASK;

		reg_mask = CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | CG_ECLK_CNTL__ECLK_DIVIDER_MASK;

	}





	r = amdgpu_atombios_get_clock_dividers(adev,

	r = amdgpu_atombios_get_clock_dividers(adev,

					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,

					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
@@ -796,24 +814,25 @@ static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 
		return r;

		return r;





	for (i = 0; i < 100; i++) {

	for (i = 0; i < 100; i++) {

		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)

		if (RREG32_SMC(reg_status) & status_mask)

			break;

			break;

		mdelay(10);

		mdelay(10);

	}

	}



	if (i == 100)

	if (i == 100)

		return -ETIMEDOUT;

		return -ETIMEDOUT;





	tmp = RREG32_SMC(ixCG_ECLK_CNTL);

	tmp = RREG32_SMC(reg_ctrl);

	tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |

	tmp &= ~reg_mask;

		CG_ECLK_CNTL__ECLK_DIVIDER_MASK);

	tmp |= dividers.post_divider;

	tmp |= dividers.post_divider;

	WREG32_SMC(ixCG_ECLK_CNTL, tmp);

	WREG32_SMC(reg_ctrl, tmp);





	for (i = 0; i < 100; i++) {

	for (i = 0; i < 100; i++) {

		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)

		if (RREG32_SMC(reg_status) & status_mask)

			break;

			break;

		mdelay(10);

		mdelay(10);

	}

	}



	if (i == 100)

	if (i == 100)

		return -ETIMEDOUT;

		return -ETIMEDOUT;