Commit 611e2dab authored by Daniel Golle's avatar Daniel Golle Committed by David S. Miller
Browse files

net: ethernet: mtk_eth_soc: reset PCS state 



Reset the internal PCS state machine when changing interface mode.
This prevents confusing the state machine when changing interface
modes, e.g. from SGMII to 2500Base-X or vice-versa.

Fixes: 7e538372 ("net: ethernet: mediatek: Re-add support SGMII")
Reviewed-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: default avatarBjørn Mork <bjorn@mork.no>
Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d8b22831

drivers/net/ethernet/mediatek/mtk_eth_soc.h

+4 −0
Original line number Diff line number Diff line
@@ -542,6 +542,10 @@ 
#define SGMII_SEND_AN_ERROR_EN		BIT(11)

#define SGMII_IF_MODE_MASK		GENMASK(5, 1)



/* Register to reset SGMII design */

#define SGMII_RESERVED_0	0x34

#define SGMII_SW_RESET		BIT(0)



/* Register to set SGMII speed, ANA RG_ Control Signals III*/

#define SGMSYS_ANA_RG_CS3	0x2028

#define RG_PHY_SPEED_MASK	(BIT(2) | BIT(3))

drivers/net/ethernet/mediatek/mtk_sgmii.c

+4 −0
Original line number Diff line number Diff line
@@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 
		regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,

				   SGMII_PHYA_PWD, SGMII_PHYA_PWD);



		/* Reset SGMII PCS state */

		regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,

				   SGMII_SW_RESET, SGMII_SW_RESET);



		if (interface == PHY_INTERFACE_MODE_2500BASEX)

			rgc3 = RG_PHY_SPEED_3_125G;

		else