Commit 6112bd00 authored by Linus Torvalds's avatar Linus Torvalds
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Pull powerpc updates from Michael Ellerman:

 - Convert to the generic mmap support (ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT)

 - Add support for outline-only KASAN with 64-bit Radix MMU (P9 or later)

 - Increase SIGSTKSZ and MINSIGSTKSZ and add support for AT_MINSIGSTKSZ

 - Enable the DAWR (Data Address Watchpoint) on POWER9 DD2.3 or later

 - Drop support for system call instruction emulation

 - Many other small features and fixes

Thanks to Alexey Kardashevskiy, Alistair Popple, Andy Shevchenko, Bagas
Sanjaya, Bjorn Helgaas, Bo Liu, Chen Huang, Christophe Leroy, Colin Ian
King, Daniel Axtens, Dwaipayan Ray, Fabiano Rosas, Finn Thain, Frank
Rowand, Fuqian Huang, Guilherme G. Piccoli, Hangyu Hua, Haowen Bai,
Haren Myneni, Hari Bathini, He Ying, Jason Wang, Jiapeng Chong, Jing
Yangyang, Joel Stanley, Julia Lawall, Kajol Jain, Kevin Hao, Krzysztof
Kozlowski, Laurent Dufour, Lv Ruyi, Madhavan Srinivasan, Magali Lemes,
Miaoqian Lin, Minghao Chi, Nathan Chancellor, Naveen N. Rao, Nicholas
Piggin, Oliver O'Halloran, Oscar Salvador, Pali Rohár, Paul Mackerras,
Peng Wu, Qing Wang, Randy Dunlap, Reza Arbab, Russell Currey, Sohaib
Mohamed, Vaibhav Jain, Vasant Hegde, Wang Qing, Wang Wensheng, Xiang
wangx, Xiaomeng Tong, Xu Wang, Yang Guang, Yang Li, Ye Bin, YueHaibing,
Yu Kuai, Zheng Bin, Zou Wei, and Zucheng Zheng.

* tag 'powerpc-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (200 commits)
  powerpc/64: Include cache.h directly in paca.h
  powerpc/64s: Only set HAVE_ARCH_UNMAPPED_AREA when CONFIG_PPC_64S_HASH_MMU is set
  powerpc/xics: Include missing header
  powerpc/powernv/pci: Drop VF MPS fixup
  powerpc/fsl_book3e: Don't set rodata RO too early
  powerpc/microwatt: Add mmu bits to device tree
  powerpc/powernv/flash: Check OPAL flash calls exist before using
  powerpc/powermac: constify device_node in of_irq_parse_oldworld()
  powerpc/powermac: add missing g5_phy_disable_cpu1() declaration
  selftests/powerpc/pmu: fix spelling mistake "mis-match" -> "mismatch"
  powerpc: Enable the DAWR on POWER9 DD2.3 and above
  powerpc/64s: Add CPU_FTRS_POWER10 to ALWAYS mask
  powerpc/64s: Add CPU_FTRS_POWER9_DD2_2 to CPU_FTRS_ALWAYS mask
  powerpc: Fix all occurences of "the the"
  selftests/powerpc/pmu/ebb: remove fixed_instruction.S
  powerpc/platforms/83xx: Use of_device_get_match_data()
  powerpc/eeh: Drop redundant spinlock initialization
  powerpc/iommu: Add missing of_node_put in iommu_init_early_dart
  powerpc/pseries/vas: Call misc_deregister if sysfs init fails
  powerpc/papr_scm: Fix leaking nvdimm_events_map elements
  ...
parents 907bb57a dcf280e6
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@@ -103,8 +103,8 @@ What: /sys/class/cxl/<afu>/api_version_compatible
Date:           September 2014
Contact:        linuxppc-dev@lists.ozlabs.org
Description:    read only
                Decimal value of the the lowest version of the userspace API
                this this kernel supports.
                Decimal value of the lowest version of the userspace API
                this kernel supports.
Users:		https://github.com/ibm-capi/libcxl


+0 −20
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* Freescale PQ3 and QorIQ based Cache SRAM

Freescale's mpc85xx and some QorIQ platforms provide an
option of configuring a part of (or full) cache memory
as SRAM. This cache SRAM representation in the device
tree should be done as under:-

Required properties:

- compatible : should be "fsl,p2020-cache-sram"
- fsl,cache-sram-ctlr-handle : points to the L2 controller
- reg : offset and length of the cache-sram.

Example:

cache-sram@fff00000 {
	fsl,cache-sram-ctlr-handle = <&L2>;
	reg = <0 0xfff00000 0 0x10000>;
	compatible = "fsl,p2020-cache-sram";
};
+17 −9
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@@ -2,15 +2,23 @@
DAWR issues on POWER9
=====================

On POWER9 the Data Address Watchpoint Register (DAWR) can cause a checkstop
if it points to cache inhibited (CI) memory. Currently Linux has no way to
distinguish CI memory when configuring the DAWR, so (for now) the DAWR is
disabled by this commit::

    commit 9654153158d3e0684a1bdb76dbababdb7111d5a0
    Author: Michael Neuling <mikey@neuling.org>
    Date:   Tue Mar 27 15:37:24 2018 +1100
    powerpc: Disable DAWR in the base POWER9 CPU features
On older POWER9 processors, the Data Address Watchpoint Register (DAWR) can
cause a checkstop if it points to cache inhibited (CI) memory. Currently Linux
has no way to distinguish CI memory when configuring the DAWR, so on affected
systems, the DAWR is disabled.

Affected processor revisions
============================

This issue is only present on processors prior to v2.3. The revision can be
found in /proc/cpuinfo::

    processor       : 0
    cpu             : POWER9, altivec supported
    clock           : 3800.000000MHz
    revision        : 2.3 (pvr 004e 1203)

On a system with the issue, the DAWR is disabled as detailed below.

Technical Details:
==================
+58 −0
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KASAN is supported on powerpc on 32-bit and Radix 64-bit only.

32 bit support
==============

KASAN is supported on both hash and nohash MMUs on 32-bit.

The shadow area sits at the top of the kernel virtual memory space above the
fixmap area and occupies one eighth of the total kernel virtual memory space.

Instrumentation of the vmalloc area is optional, unless built with modules,
in which case it is required.

64 bit support
==============

Currently, only the radix MMU is supported. There have been versions for hash
and Book3E processors floating around on the mailing list, but nothing has been
merged.

KASAN support on Book3S is a bit tricky to get right:

 - It would be good to support inline instrumentation so as to be able to catch
   stack issues that cannot be caught with outline mode.

 - Inline instrumentation requires a fixed offset.

 - Book3S runs code with translations off ("real mode") during boot, including a
   lot of generic device-tree parsing code which is used to determine MMU
   features.

 - Some code - most notably a lot of KVM code - also runs with translations off
   after boot.

 - Therefore any offset has to point to memory that is valid with
   translations on or off.

One approach is just to give up on inline instrumentation. This way boot-time
checks can be delayed until after the MMU is set is up, and we can just not
instrument any code that runs with translations off after booting. This is the
current approach.

To avoid this limitiation, the KASAN shadow would have to be placed inside the
linear mapping, using the same high-bits trick we use for the rest of the linear
mapping. This is tricky:

 - We'd like to place it near the start of physical memory. In theory we can do
   this at run-time based on how much physical memory we have, but this requires
   being able to arbitrarily relocate the kernel, which is basically the tricky
   part of KASLR. Not being game to implement both tricky things at once, this
   is hopefully something we can revisit once we get KASLR for Book3S.

 - Alternatively, we can place the shadow at the _end_ of memory, but this
   requires knowing how much contiguous physical memory a system has _at compile
   time_. This is a big hammer, and has some unfortunate consequences: inablity
   to handle discontiguous physical memory, total failure to boot on machines
   with less memory than specified, and that machines with more memory than
   specified can't use it. This was deemed unacceptable.
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@@ -1019,12 +1019,10 @@ config PAGE_SIZE_LESS_THAN_64KB
	depends on !IA64_PAGE_SIZE_64KB
	depends on !PAGE_SIZE_64KB
	depends on !PARISC_PAGE_SIZE_64KB
	depends on !PPC_64K_PAGES
	depends on PAGE_SIZE_LESS_THAN_256KB

config PAGE_SIZE_LESS_THAN_256KB
	def_bool y
	depends on !PPC_256K_PAGES
	depends on !PAGE_SIZE_256KB

# This allows to use a set of generic functions to determine mmap base
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