Commit 907bb57a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "Pretty big this time. Mostly due to (nice) Renesas refactorings.

  Core changes:

   - New helpers from Andy such as for_each_gpiochip_node() affecting
     both GPIO and pin control, improving a bunch of drivers in the
     process.

   - Pulled in Marc Zyngiers work to make IRQ chips immutable, and
     started to apply fixups on top.

  New drivers:

   - New driver for Marvell MVEBU 98DX2530.

   - New driver for Mediatek MT8195.

   - Support Qualcomm PMX65 and PM6125.

   - New driver for Qualcomm SC7280 LPASS pin control.

   - New driver for Rockchip RK3588.

   - New driver for NXP Freescale i.MXRT1170.

   - New driver for Mediatek MT6795 Helio X10.

  Improvements:

   - Several Aspeed G6 cleanups and non-critical fixes.

   - Thorought refactoring of some of the ever improving Renesas
     drivers.

   - Clean up Mediatek MT8192 bindings a bit.

   - PWM output and clock monitoring in the Ocelot LAN966x driver.

   - Thorough refactoring and cleanup of the Ralink drivers such as
     RT2880, RT3883, RT305X, MT7620, MT7621, MT7628 splitting these into
     proper sub-drivers"

* tag 'pinctrl-v5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (161 commits)
  pinctrl: apple: Use a raw spinlock for the regmap
  pinctrl: berlin: bg4ct: Use devm_platform_*ioremap_resource() APIs
  pinctrl: intel: Fix kernel doc format, i.e. add return sections
  dt-bindings: pinctrl: qcom: Drop 'maxItems' on 'wakeup-parent'
  pinctrl: starfive: Make the irqchip immutable
  pinctrl: mediatek: Add pinctrl driver for MT6795 Helio X10
  dt-bindings: pinctrl: Add MediaTek MT6795 pinctrl bindings
  pinctrl: freescale: Add i.MXRT1170 pinctrl driver support
  dt-bindings: pinctrl: add i.MXRT1170 pinctrl Documentation
  dt-bindings: pinctrl: rockchip: increase max amount of device functions
  dt-bindings: pinctrl: qcom,pmic-gpio: add 'gpio-reserved-ranges'
  dt-bindings: pinctrl: qcom,pmic-gpio: add 'input-disable'
  dt-bindings: pinctrl: qcom,pmic-gpio: describe gpio-line-names
  dt-bindings: pinctrl: qcom,pmic-gpio: fix matching pin config
  dt-bindings: pinctrl: qcom,pmic-gpio: document PM8150L and PMM8155AU
  pinctrl: qcom: spmi-gpio: Add pm6125 compatible
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm6125 compatible
  pinctrl: intel: Drop unused irqchip member in struct intel_pinctrl
  pinctrl: intel: make irq_chip immutable
  pinctrl: cherryview: Use GPIO chip pointer in chv_gpio_irq_mask_unmask()
  ...
parents ca7984df 83969805

Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt

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@@ -22,6 +22,7 @@ Properties: 
		    - "qcom,sc7280-pdc": For SC7280

		    - "qcom,sdm845-pdc": For SDM845

		    - "qcom,sm6350-pdc": For SM6350

		    - "qcom,sm8150-pdc": For SM8150

		    - "qcom,sm8250-pdc": For SM8250

		    - "qcom,sm8350-pdc": For SM8350

Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml

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@@ -76,13 +76,7 @@ additionalProperties: false 
examples:

  - |

    #include <dt-bindings/clock/aspeed-clock.h>

    apb {

        compatible = "simple-bus";

        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        syscon: scu@1e6e2000 {

    scu@1e6e2000 {

        compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";

        reg = <0x1e6e2000 0x1a8>;

        #clock-cells = <1>;
@@ -103,46 +97,3 @@ examples: 
            };

        };

    };
 


        gfx: display@1e6e6000 {

            compatible = "aspeed,ast2500-gfx", "syscon";

            reg = <0x1e6e6000 0x1000>;

            reg-io-width = <4>;

            clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;

            resets = <&syscon ASPEED_RESET_CRT1>;

            interrupts = <0x19>;

            syscon = <&syscon>;

            memory-region = <&gfx_memory>;

        };

    };



    lpc: lpc@1e789000 {

        compatible = "aspeed,ast2500-lpc", "simple-mfd";

        reg = <0x1e789000 0x1000>;



        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0x0 0x1e789000 0x1000>;



        lpc_host: lpc-host@80 {

            compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";

            reg = <0x80 0x1e0>;

            reg-io-width = <4>;



            #address-cells = <1>;

            #size-cells = <1>;

            ranges = <0x0 0x80 0x1e0>;



            lhc: lhc@20 {

                   compatible = "aspeed,ast2500-lhc";

                   reg = <0x20 0x24>, <0x48 0x8>;

            };

        };

    };



    gfx_memory: framebuffer {

        size = <0x01000000>;

        alignment = <0x01000000>;

        compatible = "shared-dma-pool";

        reusable;

    };

Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt

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* Freescale i.MX7 Dual IOMUX Controller



iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar

as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low

power state retention capabilities on gpios that are part of iomuxc-lpsr

(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for

mux and pad control settings, it shares the input select register from main

iomuxc controller for daisy chain settings, the fsl,input-sel property extends

fsl,imx-pinctrl driver to support iomuxc-lpsr controller.



iomuxc_lpsr: iomuxc-lpsr@302c0000 {

	compatible = "fsl,imx7d-iomuxc-lpsr";

	reg = <0x302c0000 0x10000>;

	fsl,input-sel = <&iomuxc>;

};



iomuxc: iomuxc@30330000 {

	compatible = "fsl,imx7d-iomuxc";

	reg = <0x30330000 0x10000>;

};



Peripherals using pads from iomuxc-lpsr support low state retention power

state, under LPSR mode GPIO's state of pads are retain.



Please refer to fsl,imx-pinctrl.txt in this directory for common binding part

and usage.



Required properties:

- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or

  "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.

- fsl,pins: each entry consists of 6 integers and represents the mux and config

  setting for one pin.  The first 5 integers <mux_reg conf_reg input_reg mux_val

  input_val> are specified using a PIN_FUNC_ID macro, which can be found in

  imx7d-pinfunc.h under device tree source folder.  The last integer CONFIG is

  the pad setting value like pull-up on this pin.  Please refer to i.MX7 Dual

  Reference Manual for detailed CONFIG settings.

- fsl,input-sel: required property for iomuxc-lpsr controller, this property is

  a phandle for main iomuxc controller which shares the input select register for

  daisy chain settings.



CONFIG bits definition:

PAD_CTL_PUS_100K_DOWN           (0 << 5)

PAD_CTL_PUS_5K_UP               (1 << 5)

PAD_CTL_PUS_47K_UP              (2 << 5)

PAD_CTL_PUS_100K_UP             (3 << 5)

PAD_CTL_PUE                     (1 << 4)

PAD_CTL_HYS                     (1 << 3)

PAD_CTL_SRE_SLOW                (1 << 2)

PAD_CTL_SRE_FAST                (0 << 2)

PAD_CTL_DSE_X1                  (0 << 0)

PAD_CTL_DSE_X4                  (1 << 0)

PAD_CTL_DSE_X2                  (2 << 0)

PAD_CTL_DSE_X6                  (3 << 0)



Examples:

While iomuxc-lpsr is intended to be used by dedicated peripherals to take

advantages of LPSR power mode, is also possible that an IP to use pads from

any of the iomux controllers. For example the I2C1 IP can use SCL pad from

iomuxc-lpsr controller and SDA pad from iomuxc controller as:



i2c1: i2c@30a20000 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>;

};



iomuxc-lpsr@302c0000 {

	compatible = "fsl,imx7d-iomuxc-lpsr";

	reg = <0x302c0000 0x10000>;

	fsl,input-sel = <&iomuxc>;



	pinctrl_i2c1_1: i2c1grp-1 {

		fsl,pins = <

			MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f

		>;

	};

};



iomuxc@30330000 {

	compatible = "fsl,imx7d-iomuxc";

	reg = <0x30330000 0x10000>;



	pinctrl_i2c1_2: i2c1grp-2 {

		fsl,pins = <

			MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f

		>;

	};

};

Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml

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# SPDX-License-Identifier: GPL-2.0

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale IMX7D IOMUX Controller



maintainers:

  - Dong Aisheng <aisheng.dong@nxp.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    oneOf:

      - enum:

          - fsl,imx7d-iomuxc

          - fsl,imx7d-iomuxc-lpsr



  reg:

    maxItems: 1



  fsl,input-sel:

    description:

      phandle for main iomuxc controller which shares the input select

      register for daisy chain settings.

    $ref: /schemas/types.yaml#/definitions/phandle



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer

          CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MX7D Reference Manual for detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_reg" indicates the offset of mux register.

            - description: |

                "conf_reg" indicates the offset of pad configuration register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_val" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.



    required:

      - fsl,pins



    additionalProperties: false



allOf:

  - $ref: "pinctrl.yaml#"



required:

  - compatible

  - reg



if:

  properties:

    compatible:

      contains:

        enum:

          - fsl,imx7d-iomuxc-lpsr



then:

  required:

    - fsl,input-sel



additionalProperties: false



examples:

  - |

    iomuxc: pinctrl@30330000 {

      compatible = "fsl,imx7d-iomuxc";

      reg = <0x30330000 0x10000>;



      pinctrl_uart5: uart5grp {

        fsl,pins =

          <0x0160 0x03D0 0x0714 0x1 0x0	0x7e>,

          <0x0164 0x03D4 0x0000 0x1 0x0	0x76>;

      };

    };

  - |

    iomuxc_lpsr: pinctrl@302c0000 {

      compatible = "fsl,imx7d-iomuxc-lpsr";

      reg = <0x302c0000 0x10000>;

      fsl,input-sel = <&iomuxc>;



      pinctrl_gpio_lpsr: gpio1-grp {

          fsl,pins =

            <0x0008 0x0038 0x0000 0x0 0x0	0x59>,

            <0x000C 0x003C 0x0000 0x0 0x0	0x59>;

        };

    };

Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MXRT1170 IOMUX Controller



maintainers:

  - Giulio Benetti <giulio.benetti@benettiengineering.com>

  - Jesse Taube <Mr.Bossman075@gmail.com>



description:

  Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory

  for common binding part and usage.



properties:

  compatible:

    const: fsl,imxrt1170-iomuxc



  reg:

    maxItems: 1



# Client device subnode's properties

patternProperties:

  'grp$':

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.

      Client device subnodes use below standard properties.



    properties:

      fsl,pins:

        description:

          each entry consists of 6 integers and represents the mux and config

          setting for one pin. The first 5 integers <mux_reg conf_reg input_reg

          mux_val input_val> are specified using a PIN_FUNC_ID macro, which can

          be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last

          integer CONFIG is the pad setting value like pull-up on this pin. Please

          refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        items:

          items:

            - description: |

                "mux_reg" indicates the offset of mux register.

            - description: |

                "conf_reg" indicates the offset of pad configuration register.

            - description: |

                "input_reg" indicates the offset of select input register.

            - description: |

                "mux_val" indicates the mux value to be applied.

            - description: |

                "input_val" indicates the select input value to be applied.

            - description: |

                "pad_setting" indicates the pad configuration value to be applied.

    required:

      - fsl,pins



    additionalProperties: false



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    iomuxc: iomuxc@400e8000 {

        compatible = "fsl,imxrt1170-iomuxc";

        reg = <0x400e8000 0x4000>;

        pinctrl_lpuart1: lpuart1grp {

            fsl,pins =

              <0x16C 0x3B0 0x620 0x0 0x0  0xf1>,

              <0x170 0x3B4 0x61C 0x0 0x0	0xf1>;

        };

    };