Commit 60017f34 authored by Ashutosh Dixit's avatar Ashutosh Dixit Committed by Joonas Lahtinen
Browse files

drm/i915/gt: Fix perf limit reasons bit positions 



Perf limit reasons bit positions were off by one.

Fixes: fa68bff7 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: stable@vger.kernel.org # v5.18+
Signed-off-by: default avatarAshutosh Dixit <ashutosh.dixit@intel.com>
Acked-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarSujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220908155821.1662110-1-ashutosh.dixit@intel.com


Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent 68d46e52

drivers/gpu/drm/i915/i915_reg.h

+8 −8
Original line number Diff line number Diff line
@@ -1858,14 +1858,14 @@ 


#define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)

#define   GT0_PERF_LIMIT_REASONS_MASK	0xde3

#define   PROCHOT_MASK			REG_BIT(1)

#define   THERMAL_LIMIT_MASK		REG_BIT(2)

#define   RATL_MASK			REG_BIT(6)

#define   VR_THERMALERT_MASK		REG_BIT(7)

#define   VR_TDC_MASK			REG_BIT(8)

#define   POWER_LIMIT_4_MASK		REG_BIT(9)

#define   POWER_LIMIT_1_MASK		REG_BIT(11)

#define   POWER_LIMIT_2_MASK		REG_BIT(12)

#define   PROCHOT_MASK			REG_BIT(0)

#define   THERMAL_LIMIT_MASK		REG_BIT(1)

#define   RATL_MASK			REG_BIT(5)

#define   VR_THERMALERT_MASK		REG_BIT(6)

#define   VR_TDC_MASK			REG_BIT(7)

#define   POWER_LIMIT_4_MASK		REG_BIT(8)

#define   POWER_LIMIT_1_MASK		REG_BIT(10)

#define   POWER_LIMIT_2_MASK		REG_BIT(11)



#define CHV_CLK_CTL1			_MMIO(0x101100)

#define VLV_CLK_CTL2			_MMIO(0x101104)