Commit 5ec0d692 authored by Tiezhu Yang's avatar Tiezhu Yang Committed by Wentao Guan
Browse files

LoongArch: Change 8 to 14 for LOONGARCH_MAX_{BRP,WRP} 

stable inclusion
from stable-v6.6.76
commit 9b7f5ef4bacea93383c18f5f0c6b77236526d9a9
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBW08Q

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=9b7f5ef4bacea93383c18f5f0c6b77236526d9a9

--------------------------------

commit f502ea618bf16d615d7dc6138c8988d3118fe750 upstream.

The maximum number of load/store watchpoints and fetch instruction
watchpoints is 14 each according to LoongArch Reference Manual, so
change 8 to 14 for the related code.

Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#control-and-status-registers-related-to-watchpoints


Cc: stable@vger.kernel.org
Fixes: edffa33c ("LoongArch: Add hardware breakpoints/watchpoints support")
Reviewed-by: default avatarWANG Xuerui <git@xen0n.name>
Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 9b7f5ef4bacea93383c18f5f0c6b77236526d9a9)
Signed-off-by: default avatarWentao Guan <guanwentao@uniontech.com>
parent c940779b

arch/loongarch/include/asm/hw_breakpoint.h

+2 −2
Original line number Diff line number Diff line
@@ -38,8 +38,8 @@ struct arch_hw_breakpoint { 
 * Limits.

 * Changing these will require modifications to the register accessors.

 */

#define LOONGARCH_MAX_BRP		8

#define LOONGARCH_MAX_WRP		8

#define LOONGARCH_MAX_BRP		14

#define LOONGARCH_MAX_WRP		14



/* Virtual debug register bases. */

#define CSR_CFG_ADDR	0

arch/loongarch/include/asm/loongarch.h

+60 −0
Original line number Diff line number Diff line
@@ -959,6 +959,36 @@ 
#define LOONGARCH_CSR_DB7CTRL		0x34a	/* data breakpoint 7 control */

#define LOONGARCH_CSR_DB7ASID		0x34b	/* data breakpoint 7 asid */



#define LOONGARCH_CSR_DB8ADDR		0x350	/* data breakpoint 8 address */

#define LOONGARCH_CSR_DB8MASK		0x351	/* data breakpoint 8 mask */

#define LOONGARCH_CSR_DB8CTRL		0x352	/* data breakpoint 8 control */

#define LOONGARCH_CSR_DB8ASID		0x353	/* data breakpoint 8 asid */



#define LOONGARCH_CSR_DB9ADDR		0x358	/* data breakpoint 9 address */

#define LOONGARCH_CSR_DB9MASK		0x359	/* data breakpoint 9 mask */

#define LOONGARCH_CSR_DB9CTRL		0x35a	/* data breakpoint 9 control */

#define LOONGARCH_CSR_DB9ASID		0x35b	/* data breakpoint 9 asid */



#define LOONGARCH_CSR_DB10ADDR		0x360	/* data breakpoint 10 address */

#define LOONGARCH_CSR_DB10MASK		0x361	/* data breakpoint 10 mask */

#define LOONGARCH_CSR_DB10CTRL		0x362	/* data breakpoint 10 control */

#define LOONGARCH_CSR_DB10ASID		0x363	/* data breakpoint 10 asid */



#define LOONGARCH_CSR_DB11ADDR		0x368	/* data breakpoint 11 address */

#define LOONGARCH_CSR_DB11MASK		0x369	/* data breakpoint 11 mask */

#define LOONGARCH_CSR_DB11CTRL		0x36a	/* data breakpoint 11 control */

#define LOONGARCH_CSR_DB11ASID		0x36b	/* data breakpoint 11 asid */



#define LOONGARCH_CSR_DB12ADDR		0x370	/* data breakpoint 12 address */

#define LOONGARCH_CSR_DB12MASK		0x371	/* data breakpoint 12 mask */

#define LOONGARCH_CSR_DB12CTRL		0x372	/* data breakpoint 12 control */

#define LOONGARCH_CSR_DB12ASID		0x373	/* data breakpoint 12 asid */



#define LOONGARCH_CSR_DB13ADDR		0x378	/* data breakpoint 13 address */

#define LOONGARCH_CSR_DB13MASK		0x379	/* data breakpoint 13 mask */

#define LOONGARCH_CSR_DB13CTRL		0x37a	/* data breakpoint 13 control */

#define LOONGARCH_CSR_DB13ASID		0x37b	/* data breakpoint 13 asid */



#define LOONGARCH_CSR_FWPC		0x380	/* instruction breakpoint config */

#define LOONGARCH_CSR_FWPS		0x381	/* instruction breakpoint status */
@@ -1002,6 +1032,36 @@ 
#define LOONGARCH_CSR_IB7CTRL		0x3ca	/* inst breakpoint 7 control */

#define LOONGARCH_CSR_IB7ASID		0x3cb	/* inst breakpoint 7 asid */



#define LOONGARCH_CSR_IB8ADDR		0x3d0	/* inst breakpoint 8 address */

#define LOONGARCH_CSR_IB8MASK		0x3d1	/* inst breakpoint 8 mask */

#define LOONGARCH_CSR_IB8CTRL		0x3d2	/* inst breakpoint 8 control */

#define LOONGARCH_CSR_IB8ASID		0x3d3	/* inst breakpoint 8 asid */



#define LOONGARCH_CSR_IB9ADDR		0x3d8	/* inst breakpoint 9 address */

#define LOONGARCH_CSR_IB9MASK		0x3d9	/* inst breakpoint 9 mask */

#define LOONGARCH_CSR_IB9CTRL		0x3da	/* inst breakpoint 9 control */

#define LOONGARCH_CSR_IB9ASID		0x3db	/* inst breakpoint 9 asid */



#define LOONGARCH_CSR_IB10ADDR		0x3e0	/* inst breakpoint 10 address */

#define LOONGARCH_CSR_IB10MASK		0x3e1	/* inst breakpoint 10 mask */

#define LOONGARCH_CSR_IB10CTRL		0x3e2	/* inst breakpoint 10 control */

#define LOONGARCH_CSR_IB10ASID		0x3e3	/* inst breakpoint 10 asid */



#define LOONGARCH_CSR_IB11ADDR		0x3e8	/* inst breakpoint 11 address */

#define LOONGARCH_CSR_IB11MASK		0x3e9	/* inst breakpoint 11 mask */

#define LOONGARCH_CSR_IB11CTRL		0x3ea	/* inst breakpoint 11 control */

#define LOONGARCH_CSR_IB11ASID		0x3eb	/* inst breakpoint 11 asid */



#define LOONGARCH_CSR_IB12ADDR		0x3f0	/* inst breakpoint 12 address */

#define LOONGARCH_CSR_IB12MASK		0x3f1	/* inst breakpoint 12 mask */

#define LOONGARCH_CSR_IB12CTRL		0x3f2	/* inst breakpoint 12 control */

#define LOONGARCH_CSR_IB12ASID		0x3f3	/* inst breakpoint 12 asid */



#define LOONGARCH_CSR_IB13ADDR		0x3f8	/* inst breakpoint 13 address */

#define LOONGARCH_CSR_IB13MASK		0x3f9	/* inst breakpoint 13 mask */

#define LOONGARCH_CSR_IB13CTRL		0x3fa	/* inst breakpoint 13 control */

#define LOONGARCH_CSR_IB13ASID		0x3fb	/* inst breakpoint 13 asid */



#define LOONGARCH_CSR_DEBUG		0x500	/* debug config */

#define LOONGARCH_CSR_DERA		0x501	/* debug era */

#define LOONGARCH_CSR_DESAVE		0x502	/* debug save */

arch/loongarch/kernel/hw_breakpoint.c

+14 −2
Original line number Diff line number Diff line
@@ -51,7 +51,13 @@ int hw_breakpoint_slots(int type) 
	READ_WB_REG_CASE(OFF, 4, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 5, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 6, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 7, REG, T, VAL);

	READ_WB_REG_CASE(OFF, 7, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 8, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 9, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 10, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 11, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 12, REG, T, VAL);		\

	READ_WB_REG_CASE(OFF, 13, REG, T, VAL);



#define GEN_WRITE_WB_REG_CASES(OFF, REG, T, VAL)	\

	WRITE_WB_REG_CASE(OFF, 0, REG, T, VAL);		\
@@ -61,7 +67,13 @@ int hw_breakpoint_slots(int type) 
	WRITE_WB_REG_CASE(OFF, 4, REG, T, VAL);		\

	WRITE_WB_REG_CASE(OFF, 5, REG, T, VAL);		\

	WRITE_WB_REG_CASE(OFF, 6, REG, T, VAL);		\

	WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);

	WRITE_WB_REG_CASE(OFF, 7, REG, T, VAL);		\

	WRITE_WB_REG_CASE(OFF, 8, REG, T, VAL);		\

	WRITE_WB_REG_CASE(OFF, 9, REG, T, VAL);		\

	WRITE_WB_REG_CASE(OFF, 10, REG, T, VAL);	\

	WRITE_WB_REG_CASE(OFF, 11, REG, T, VAL);	\

	WRITE_WB_REG_CASE(OFF, 12, REG, T, VAL);	\

	WRITE_WB_REG_CASE(OFF, 13, REG, T, VAL);



static u64 read_wb_reg(int reg, int n, int t)

{