Commit edffa33c authored by Qing Zhang's avatar Qing Zhang Committed by Huacai Chen
Browse files

LoongArch: Add hardware breakpoints/watchpoints support 



Use perf framework to manage hardware instruction and data breakpoints.

LoongArch defines hardware watchpoint functions for instruction fetch
and memory load/store operations. After the software configures hardware
watchpoints, the processor hardware will monitor the access address of
the instruction fetch and load/store operation, and trigger an exception
of the watchpoint when it meets the conditions set by the watchpoint.

The hardware monitoring points for instruction fetching and load/store
operations each have a register for the overall configuration of all
monitoring points, a register for recording the status of all monitoring
points, and four registers required for configuration of each watchpoint
individually.

Signed-off-by: default avatarQing Zhang <zhangqing@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 35c94fab

arch/loongarch/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ config LOONGARCH 
	select HAVE_FUNCTION_GRAPH_TRACER

	select HAVE_FUNCTION_TRACER

	select HAVE_GENERIC_VDSO

	select HAVE_HW_BREAKPOINT if PERF_EVENTS

	select HAVE_IOREMAP_PROT

	select HAVE_IRQ_EXIT_ON_IRQ_STACK

	select HAVE_IRQ_TIME_ACCOUNTING

arch/loongarch/include/asm/hw_breakpoint.h

0 → 100644
+145 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited

 */

#ifndef __ASM_HW_BREAKPOINT_H

#define __ASM_HW_BREAKPOINT_H



#include <asm/loongarch.h>



#ifdef __KERNEL__



/* Breakpoint */

#define LOONGARCH_BREAKPOINT_EXECUTE		(0 << 0)



/* Watchpoints */

#define LOONGARCH_BREAKPOINT_LOAD		(1 << 0)

#define LOONGARCH_BREAKPOINT_STORE		(1 << 1)



struct arch_hw_breakpoint_ctrl {

	u32 __reserved	: 28,

	len		: 2,

	type		: 2;

};



struct arch_hw_breakpoint {

	u64 address;

	u64 mask;

	struct arch_hw_breakpoint_ctrl ctrl;

};



/* Lengths */

#define LOONGARCH_BREAKPOINT_LEN_1    0b11

#define LOONGARCH_BREAKPOINT_LEN_2    0b10

#define LOONGARCH_BREAKPOINT_LEN_4    0b01

#define LOONGARCH_BREAKPOINT_LEN_8    0b00



/*

 * Limits.

 * Changing these will require modifications to the register accessors.

 */

#define LOONGARCH_MAX_BRP		8

#define LOONGARCH_MAX_WRP		8



/* Virtual debug register bases. */

#define CSR_CFG_ADDR	0

#define CSR_CFG_MASK	(CSR_CFG_ADDR + LOONGARCH_MAX_BRP)

#define CSR_CFG_CTRL	(CSR_CFG_MASK + LOONGARCH_MAX_BRP)

#define CSR_CFG_ASID	(CSR_CFG_CTRL + LOONGARCH_MAX_WRP)



/* Debug register names. */

#define LOONGARCH_CSR_NAME_ADDR	ADDR

#define LOONGARCH_CSR_NAME_MASK	MASK

#define LOONGARCH_CSR_NAME_CTRL	CTRL

#define LOONGARCH_CSR_NAME_ASID	ASID



/* Accessor macros for the debug registers. */

#define LOONGARCH_CSR_WATCH_READ(N, REG, T, VAL)			\

do {								\

	if (T == 0)						\

		VAL = csr_read64(LOONGARCH_CSR_##IB##N##REG);	\

	else							\

		VAL = csr_read64(LOONGARCH_CSR_##DB##N##REG);	\

} while (0)



#define LOONGARCH_CSR_WATCH_WRITE(N, REG, T, VAL)			\

do {								\

	if (T == 0)						\

		csr_write64(VAL, LOONGARCH_CSR_##IB##N##REG);	\

	else							\

		csr_write64(VAL, LOONGARCH_CSR_##DB##N##REG);	\

} while (0)



/* Exact number */

#define CSR_FWPC_NUM		0x3f

#define CSR_MWPC_NUM		0x3f



#define CTRL_PLV_ENABLE		0x1e



#define MWPnCFG3_LoadEn		8

#define MWPnCFG3_StoreEn	9



#define MWPnCFG3_Type_mask	0x3

#define MWPnCFG3_Size_mask	0x3



static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)

{

	return (ctrl.len << 10) | (ctrl.type << 8);

}



static inline void decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl)

{

	reg >>= 8;

	ctrl->type = reg & MWPnCFG3_Type_mask;

	reg >>= 2;

	ctrl->len  = reg & MWPnCFG3_Size_mask;

}



struct task_struct;

struct notifier_block;

struct perf_event;

struct perf_event_attr;



extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,

				  int *gen_len, int *gen_type, int *offset);

extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);

extern int hw_breakpoint_arch_parse(struct perf_event *bp,

				    const struct perf_event_attr *attr,

				    struct arch_hw_breakpoint *hw);

extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,

					   unsigned long val, void *data);



extern int arch_install_hw_breakpoint(struct perf_event *bp);

extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);

extern int hw_breakpoint_slots(int type);

extern void hw_breakpoint_pmu_read(struct perf_event *bp);



void breakpoint_handler(struct pt_regs *regs);

void watchpoint_handler(struct pt_regs *regs);



#ifdef CONFIG_HAVE_HW_BREAKPOINT

extern void ptrace_hw_copy_thread(struct task_struct *task);

extern void hw_breakpoint_thread_switch(struct task_struct *next);

#else

static inline void ptrace_hw_copy_thread(struct task_struct *task)

{

}

static inline void hw_breakpoint_thread_switch(struct task_struct *next)

{

}

#endif



/* Determine number of BRP registers available. */

static inline int get_num_brps(void)

{

	return csr_read64(LOONGARCH_CSR_FWPC) & CSR_FWPC_NUM;

}



/* Determine number of WRP registers available. */

static inline int get_num_wrps(void)

{

	return csr_read64(LOONGARCH_CSR_MWPC) & CSR_MWPC_NUM;

}



#endif	/* __KERNEL__ */

#endif	/* __ASM_BREAKPOINT_H */

arch/loongarch/include/asm/loongarch.h

+16 −16
Original line number Diff line number Diff line
@@ -970,42 +970,42 @@ static __always_inline void iocsr_write64(u64 val, u32 reg) 


#define LOONGARCH_CSR_DB0ADDR		0x310	/* data breakpoint 0 address */

#define LOONGARCH_CSR_DB0MASK		0x311	/* data breakpoint 0 mask */

#define LOONGARCH_CSR_DB0CTL		0x312	/* data breakpoint 0 control */

#define LOONGARCH_CSR_DB0CTRL		0x312	/* data breakpoint 0 control */

#define LOONGARCH_CSR_DB0ASID		0x313	/* data breakpoint 0 asid */



#define LOONGARCH_CSR_DB1ADDR		0x318	/* data breakpoint 1 address */

#define LOONGARCH_CSR_DB1MASK		0x319	/* data breakpoint 1 mask */

#define LOONGARCH_CSR_DB1CTL		0x31a	/* data breakpoint 1 control */

#define LOONGARCH_CSR_DB1CTRL		0x31a	/* data breakpoint 1 control */

#define LOONGARCH_CSR_DB1ASID		0x31b	/* data breakpoint 1 asid */



#define LOONGARCH_CSR_DB2ADDR		0x320	/* data breakpoint 2 address */

#define LOONGARCH_CSR_DB2MASK		0x321	/* data breakpoint 2 mask */

#define LOONGARCH_CSR_DB2CTL		0x322	/* data breakpoint 2 control */

#define LOONGARCH_CSR_DB2CTRL		0x322	/* data breakpoint 2 control */

#define LOONGARCH_CSR_DB2ASID		0x323	/* data breakpoint 2 asid */



#define LOONGARCH_CSR_DB3ADDR		0x328	/* data breakpoint 3 address */

#define LOONGARCH_CSR_DB3MASK		0x329	/* data breakpoint 3 mask */

#define LOONGARCH_CSR_DB3CTL		0x32a	/* data breakpoint 3 control */

#define LOONGARCH_CSR_DB3CTRL		0x32a	/* data breakpoint 3 control */

#define LOONGARCH_CSR_DB3ASID		0x32b	/* data breakpoint 3 asid */



#define LOONGARCH_CSR_DB4ADDR		0x330	/* data breakpoint 4 address */

#define LOONGARCH_CSR_DB4MASK		0x331	/* data breakpoint 4 maks */

#define LOONGARCH_CSR_DB4CTL		0x332	/* data breakpoint 4 control */

#define LOONGARCH_CSR_DB4CTRL		0x332	/* data breakpoint 4 control */

#define LOONGARCH_CSR_DB4ASID		0x333	/* data breakpoint 4 asid */



#define LOONGARCH_CSR_DB5ADDR		0x338	/* data breakpoint 5 address */

#define LOONGARCH_CSR_DB5MASK		0x339	/* data breakpoint 5 mask */

#define LOONGARCH_CSR_DB5CTL		0x33a	/* data breakpoint 5 control */

#define LOONGARCH_CSR_DB5CTRL		0x33a	/* data breakpoint 5 control */

#define LOONGARCH_CSR_DB5ASID		0x33b	/* data breakpoint 5 asid */



#define LOONGARCH_CSR_DB6ADDR		0x340	/* data breakpoint 6 address */

#define LOONGARCH_CSR_DB6MASK		0x341	/* data breakpoint 6 mask */

#define LOONGARCH_CSR_DB6CTL		0x342	/* data breakpoint 6 control */

#define LOONGARCH_CSR_DB6CTRL		0x342	/* data breakpoint 6 control */

#define LOONGARCH_CSR_DB6ASID		0x343	/* data breakpoint 6 asid */



#define LOONGARCH_CSR_DB7ADDR		0x348	/* data breakpoint 7 address */

#define LOONGARCH_CSR_DB7MASK		0x349	/* data breakpoint 7 mask */

#define LOONGARCH_CSR_DB7CTL		0x34a	/* data breakpoint 7 control */

#define LOONGARCH_CSR_DB7CTRL		0x34a	/* data breakpoint 7 control */

#define LOONGARCH_CSR_DB7ASID		0x34b	/* data breakpoint 7 asid */



#define LOONGARCH_CSR_FWPC		0x380	/* instruction breakpoint config */
@@ -1013,42 +1013,42 @@ static __always_inline void iocsr_write64(u64 val, u32 reg) 


#define LOONGARCH_CSR_IB0ADDR		0x390	/* inst breakpoint 0 address */

#define LOONGARCH_CSR_IB0MASK		0x391	/* inst breakpoint 0 mask */

#define LOONGARCH_CSR_IB0CTL		0x392	/* inst breakpoint 0 control */

#define LOONGARCH_CSR_IB0CTRL		0x392	/* inst breakpoint 0 control */

#define LOONGARCH_CSR_IB0ASID		0x393	/* inst breakpoint 0 asid */



#define LOONGARCH_CSR_IB1ADDR		0x398	/* inst breakpoint 1 address */

#define LOONGARCH_CSR_IB1MASK		0x399	/* inst breakpoint 1 mask */

#define LOONGARCH_CSR_IB1CTL		0x39a	/* inst breakpoint 1 control */

#define LOONGARCH_CSR_IB1CTRL		0x39a	/* inst breakpoint 1 control */

#define LOONGARCH_CSR_IB1ASID		0x39b	/* inst breakpoint 1 asid */



#define LOONGARCH_CSR_IB2ADDR		0x3a0	/* inst breakpoint 2 address */

#define LOONGARCH_CSR_IB2MASK		0x3a1	/* inst breakpoint 2 mask */

#define LOONGARCH_CSR_IB2CTL		0x3a2	/* inst breakpoint 2 control */

#define LOONGARCH_CSR_IB2CTRL		0x3a2	/* inst breakpoint 2 control */

#define LOONGARCH_CSR_IB2ASID		0x3a3	/* inst breakpoint 2 asid */



#define LOONGARCH_CSR_IB3ADDR		0x3a8	/* inst breakpoint 3 address */

#define LOONGARCH_CSR_IB3MASK		0x3a9	/* breakpoint 3 mask */

#define LOONGARCH_CSR_IB3CTL		0x3aa	/* inst breakpoint 3 control */

#define LOONGARCH_CSR_IB3CTRL		0x3aa	/* inst breakpoint 3 control */

#define LOONGARCH_CSR_IB3ASID		0x3ab	/* inst breakpoint 3 asid */



#define LOONGARCH_CSR_IB4ADDR		0x3b0	/* inst breakpoint 4 address */

#define LOONGARCH_CSR_IB4MASK		0x3b1	/* inst breakpoint 4 mask */

#define LOONGARCH_CSR_IB4CTL		0x3b2	/* inst breakpoint 4 control */

#define LOONGARCH_CSR_IB4CTRL		0x3b2	/* inst breakpoint 4 control */

#define LOONGARCH_CSR_IB4ASID		0x3b3	/* inst breakpoint 4 asid */



#define LOONGARCH_CSR_IB5ADDR		0x3b8	/* inst breakpoint 5 address */

#define LOONGARCH_CSR_IB5MASK		0x3b9	/* inst breakpoint 5 mask */

#define LOONGARCH_CSR_IB5CTL		0x3ba	/* inst breakpoint 5 control */

#define LOONGARCH_CSR_IB5CTRL		0x3ba	/* inst breakpoint 5 control */

#define LOONGARCH_CSR_IB5ASID		0x3bb	/* inst breakpoint 5 asid */



#define LOONGARCH_CSR_IB6ADDR		0x3c0	/* inst breakpoint 6 address */

#define LOONGARCH_CSR_IB6MASK		0x3c1	/* inst breakpoint 6 mask */

#define LOONGARCH_CSR_IB6CTL		0x3c2	/* inst breakpoint 6 control */

#define LOONGARCH_CSR_IB6CTRL		0x3c2	/* inst breakpoint 6 control */

#define LOONGARCH_CSR_IB6ASID		0x3c3	/* inst breakpoint 6 asid */



#define LOONGARCH_CSR_IB7ADDR		0x3c8	/* inst breakpoint 7 address */

#define LOONGARCH_CSR_IB7MASK		0x3c9	/* inst breakpoint 7 mask */

#define LOONGARCH_CSR_IB7CTL		0x3ca	/* inst breakpoint 7 control */

#define LOONGARCH_CSR_IB7CTRL		0x3ca	/* inst breakpoint 7 control */

#define LOONGARCH_CSR_IB7ASID		0x3cb	/* inst breakpoint 7 asid */



#define LOONGARCH_CSR_DEBUG		0x500	/* debug config */

arch/loongarch/include/asm/processor.h

+9 −6
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 


#include <asm/cpu.h>

#include <asm/cpu-info.h>

#include <asm/hw_breakpoint.h>

#include <asm/loongarch.h>

#include <asm/vdso/processor.h>

#include <uapi/asm/ptrace.h>
@@ -127,10 +128,14 @@ struct thread_struct { 
	struct loongarch_vdso_info *vdso;



	/*

	 * FPU & vector registers, must be at last because

	 * they are conditionally copied at fork().

	 * FPU & vector registers, must be at the last of inherited

	 * context because they are conditionally copied at fork().

	 */

	struct loongarch_fpu fpu FPU_ALIGN;



	/* Hardware breakpoints pinned to this task. */

	struct perf_event *hbp_break[LOONGARCH_MAX_BRP];

	struct perf_event *hbp_watch[LOONGARCH_MAX_WRP];

};



#define thread_saved_ra(tsk)	(tsk->thread.sched_ra)
@@ -172,6 +177,8 @@ struct thread_struct { 
		.fcc		= 0,				\

		.fpr		= {{{0,},},},			\

	},							\

	.hbp_break		= {0},				\

	.hbp_watch		= {0},				\

}



struct task_struct;
@@ -184,10 +191,6 @@ extern unsigned long boot_option_idle_override; 
 */

extern void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp);



static inline void flush_thread(void)

{

}



unsigned long __get_wchan(struct task_struct *p);



#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \

arch/loongarch/include/asm/switch_to.h

+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ extern asmlinkage struct task_struct *__switch_to(struct task_struct *prev, 
#define switch_to(prev, next, last)						\

do {										\

	lose_fpu_inatomic(1, prev);						\

	hw_breakpoint_thread_switch(next);					\

	(last) = __switch_to(prev, next, task_thread_info(next),		\

		 __builtin_return_address(0), __builtin_frame_address(0));	\

} while (0)