Unverified Commit 5e64ee42 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynqmp-dt-for-v6.5' of https://github.com/Xilinx/linux-xlnx into soc/dt 

arm64: ZynqMP DT changes for v6.5

Various small fixes and cleanups to be aligned with the latest dt-schema.

Other major changes are:
- Wire mali-400 gpu
- Change board name for zcu1275
- Use ethernet-phy-id to handle ETH phy reset properly
- Switch to amd.com emails
- Update people in DT bindings

* tag 'zynqmp-dt-for-v6.5' of https://github.com/Xilinx/linux-xlnx: (33 commits)
  dt-bindings: usb: xilinx: Replace Manish by Piyush
  dt-bindings: xilinx: Remove Rajan, Jolly and Manish
  arm64: zynqmp: Used fixed-partitions for QSPI in k26
  arm64: zynqmp: Add pmu interrupt-affinity
  arm64: zynqmp: Set qspi tx-buswidth to 4
  arm64: zynqmp: Fix usb node drive strength and slew rate
  arm64: zynqmp: Describe TI phy as ethernet-phy-id
  arm64: zynqmp: Switch to amd.com emails
  arm64: zynqmp: Convert kv260-revA overlay to ASCII text
  dt-bindings: xilinx: Switch xilinx.com emails to amd.com
  arm64: xilinx: Use zynqmp prefix for SOM dt overlays
  arm64: zynqmp: Add phase tags marking
  arm64: zynqmp: Describe bus-width for SD card on KV260
  arm64: zynqmp: Enable AMS on SOM and other zcu10x boards
  arm64: zynqmp: Enable DP driver for SOMs
  arm64: zynqmp: Setup clock for DP and DPDMA
  arm64: zynqmp: Switch to ethernet-phy-id in kv260
  arm64: zynqmp: Disable USB3.0 for zc1751-xm016-dc2
  arm64: zynqmp: Add pinctrl emmc description to SM-K26
  arm64: zynqmp: Add gpio labels for modepin gpio
  ...

Link: https://lore.kernel.org/r/CAHTX3d+2s_KmCnd=x5hydGb+LYoznAzYGTizvqqN2NFmrBurfw@mail.gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents c9a5aa0e 067bf44d

Documentation/devicetree/bindings/arm/xilinx.yaml

+4 −4
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx Zynq Platforms



maintainers:

  - Michal Simek <michal.simek@xilinx.com>

  - Michal Simek <michal.simek@amd.com>



description: |

  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
@@ -61,10 +61,10 @@ properties: 
          - const: xlnx,zynqmp-zc1254

          - const: xlnx,zynqmp



      - description: Xilinx internal board zc1275

      - description: Xilinx evaluation board zcu1275

        items:

          - const: xlnx,zynqmp-zc1275-revA

          - const: xlnx,zynqmp-zc1275

          - const: xlnx,zynqmp-zcu1275-revA

          - const: xlnx,zynqmp-zcu1275

          - const: xlnx,zynqmp



      - description: Xilinx 96boards compatible board zcu100

Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml

+1 −1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Ceva AHCI SATA Controller



maintainers:

  - Piyush Mehta <piyush.mehta@xilinx.com>

  - Piyush Mehta <piyush.mehta@amd.com>



description: |

  The Ceva SATA controller mostly conforms to the AHCI interface with some

Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx clocking wizard



maintainers:

  - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>

  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>



description:

  The clocking wizard is a soft ip clocking block of Xilinx versal. It

Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml

+1 −3
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@@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx Versal clock controller



maintainers:

  - Michal Simek <michal.simek@xilinx.com>

  - Jolly Shah <jolly.shah@xilinx.com>

  - Rajan Vaja <rajan.vaja@xilinx.com>

  - Michal Simek <michal.simek@amd.com>



description: |

  The clock controller is a hardware block of Xilinx versal clock tree. It

Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml

+2 −2
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@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Xilinx ZynqMP AES-GCM Hardware Accelerator



maintainers:

  - Kalyani Akula <kalyani.akula@xilinx.com>

  - Michal Simek <michal.simek@xilinx.com>

  - Kalyani Akula <kalyani.akula@amd.com>

  - Michal Simek <michal.simek@amd.com>



description: |

  The ZynqMP AES-GCM hardened cryptographic accelerator is used to