Unverified Commit c9a5aa0e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'riscv-dt-for-v6.5' of... 

Merge tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into soc/dt

RISC-V Devicetrees for v6.5

StarFive:
Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P
being power, support for the JH7110. PMIC and frequency scaling support
for the JH7110 equipped VisionFive 2.
Most of the DT bits for the JH7110, and the SBCs using it, are pending
support for one of the clock controllers, so it's a smaller set of
changes than I would have hoped for.

Misc:
Pick up some dt-binding cleanup that Palmer assigned to me & had no
uptake from the respective maintainers. My powers of estimation failed
me again, with part of my motivation for picking them up being the
addition of new platforms that ended up not making it. Hopefully next
window for those, as they were relatively close.
Exclude the Allwinner and Renesas subdirectories from the Misc.
MAINTAINERS entry, since I do not take care of those.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Add cpu scaling for JH7110 SoC
  riscv: dts: starfive: Enable axp15060 pmic for cpufreq
  dt-bindings: interrupt-controller: sifive,plic: Sort compatible values
  dt-bindings: timer: sifive,clint: Clean up compatible value section
  riscv: dts: starfive: jh7110: Add watchdog node
  riscv: dts: starfive: jh7100: Add watchdog node
  riscv: dts: starfive: Add PMU controller node
  MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry

Link: https://lore.kernel.org/r/20230612-fasting-floss-0bc05a08bc7a@spud


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 12109610 e2c510d6

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

+1 −1
Original line number Diff line number Diff line
@@ -57,10 +57,10 @@ properties: 
          - const: andestech,nceplic100

      - items:

          - enum:

              - canaan,k210-plic

              - sifive,fu540-c000-plic

              - starfive,jh7100-plic

              - starfive,jh7110-plic

              - canaan,k210-plic

          - const: sifive,plic-1.0.0

      - items:

          - enum:

Documentation/devicetree/bindings/timer/sifive,clint.yaml

+8 −13
Original line number Diff line number Diff line
@@ -29,11 +29,11 @@ properties: 
    oneOf:

      - items:

          - enum:

              - sifive,fu540-c000-clint

              - starfive,jh7100-clint

              - starfive,jh7110-clint

              - canaan,k210-clint

          - const: sifive,clint0

              - canaan,k210-clint       # Canaan Kendryte K210

              - sifive,fu540-c000-clint # SiFive FU540

              - starfive,jh7100-clint   # StarFive JH7100

              - starfive,jh7110-clint   # StarFive JH7110

          - const: sifive,clint0        # SiFive CLINT v0 IP block

      - items:

          - enum:

              - allwinner,sun20i-d1-clint
@@ -45,14 +45,9 @@ properties: 
        description: For the QEMU virt machine only



    description:

      Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".

      Supported compatible strings are -

      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated

      onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive

      CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and

      "sifive,clint0" for the SiFive CLINT v0 IP block with no chip

      integration tweaks.

      Please refer to sifive-blocks-ip-versioning.txt for details

      Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"

      when compatible with a SiFive CLINT.  Please refer to

      sifive-blocks-ip-versioning.txt for details regarding the latter.



  reg:

    maxItems: 1

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -18150,6 +18150,8 @@ Q: https://patchwork.kernel.org/project/linux-riscv/list/ 
T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/

F:	Documentation/devicetree/bindings/riscv/

F:	arch/riscv/boot/dts/

X:	arch/riscv/boot/dts/allwinner/

X:	arch/riscv/boot/dts/renesas/









RISC-V PMU DRIVERS









M:	Atish Patra <atishp@atishpatra.org>

























arch/riscv/boot/dts/starfive/jh7100.dtsi



+10
−0






























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@@ -238,5 +238,15 @@







			#size-cells = <0>;









			status = "disabled";









		};



















		watchdog@12480000 {









			compatible = "starfive,jh7100-wdt";









			reg = <0x0 0x12480000 0x0 0x10000>;









			clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,









				 <&clkgen JH7100_CLK_WDT_CORE>;









			clock-names = "apb", "core";









			resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,









				 <&rstgen JH7100_RSTN_WDT>;









		};









	};









};
























arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi



+33
−0






























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@@ -114,6 +114,23 @@







	pinctrl-names = "default";









	pinctrl-0 = <&i2c5_pins>;









	status = "okay";



















	axp15060: pmic@36 {









		compatible = "x-powers,axp15060";









		reg = <0x36>;









		interrupts = <0>;









		interrupt-controller;









		#interrupt-cells = <1>;



















		regulators {









			vdd_cpu: dcdc2 {









				regulator-always-on;









				regulator-min-microvolt = <500000>;









				regulator-max-microvolt = <1540000>;









				regulator-name = "vdd-cpu";









			};









		};









	};









};



















&i2c6 {








@@ -213,3 +230,19 @@







	pinctrl-0 = <&uart0_pins>;









	status = "okay";









};



















&U74_1 {









	cpu-supply = <&vdd_cpu>;









};



















&U74_2 {









	cpu-supply = <&vdd_cpu>;









};



















&U74_3 {









	cpu-supply = <&vdd_cpu>;









};



















&U74_4 {









	cpu-supply = <&vdd_cpu>;









};