!1048 spi: dw: Add support for 32-bits max xfer size

Merge Pull Request from: @lujunhuaHW 
 
The Synopsis DesignWare DW_apb_ssi specifications version 3.23 onward
define a 32-bits maximum transfer size synthesis parameter
(SSI_MAX_XFER_SIZE=32) in addition to the legacy 16-bits configuration
(SSI_MAX_XFER_SIZE=16) for SPI controllers. When SSI_MAX_XFER_SIZE=32,
the layout of the ctrlr0 register changes, moving the data frame format
field from bits [3..0] to bits [16..20], and the RX/TX FIFO word size
can be up to 32-bits.
 
 
Link:https://gitee.com/openeuler/kernel/pulls/1048

 

Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>