Commit 5e061a4d authored by Eryk Brol's avatar Eryk Brol Committed by Alex Deucher
Browse files

drm/amd/display: Rename bytes_pp to the correct bits_pp 



[Why]
Struct dcn_dsc_state is used for reading current state
and parameters of DSC on a pipe, the target rate parameter
uses bytes per pixel even though its reading BITS_PER_PIXEL
register.

[How]
Changing it to Bits Per Pixel for consistency.

Signed-off-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarMikita Lipski <mikita.lipski@amd.com>
Reviewed-by: default avatarMikita Lipski <Mikita.Lipski@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7c146177

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -1186,7 +1186,7 @@ static ssize_t dp_dsc_bytes_per_pixel_read(struct file *f, char __user *buf, 


	snprintf(rd_buf_ptr, str_len,

		"%d\n",

		dsc_state.dsc_bytes_per_pixel);

		dsc_state.dsc_bits_per_pixel);

	rd_buf_ptr += str_len;



	while (size) {

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+3 −1
Original line number Diff line number Diff line
@@ -390,6 +390,8 @@ void dcn10_log_hw_state(struct dc *dc, 
	}

	DTN_INFO("\n");



	// dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel

	// TODO: Update golden log header to reflect this name change

	DTN_INFO("DSC: CLOCK_EN  SLICE_WIDTH  Bytes_pp\n");

	for (i = 0; i < pool->res_cap->num_dsc; i++) {

		struct display_stream_compressor *dsc = pool->dscs[i];
@@ -400,7 +402,7 @@ void dcn10_log_hw_state(struct dc *dc, 
		dsc->inst,

			s.dsc_clock_en,

			s.dsc_slice_width,

			s.dsc_bytes_per_pixel);

			s.dsc_bits_per_pixel);

		DTN_INFO("\n");

	}

	DTN_INFO("\n");

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c

+1 −1
Original line number Diff line number Diff line
@@ -156,7 +156,7 @@ static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_ds 


	REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);

	REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);

	REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel);

	REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);

	REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);

	REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);

	REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);

drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ struct dsc_optc_config { 
struct dcn_dsc_state {

	uint32_t dsc_clock_en;

	uint32_t dsc_slice_width;

	uint32_t dsc_bytes_per_pixel;

	uint32_t dsc_bits_per_pixel;

	uint32_t dsc_slice_height;

	uint32_t dsc_pic_width;

	uint32_t dsc_pic_height;