Commit 7c146177 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: Clean up global sync param retrieval 



[Why]
This change replaces older looping code in favor of these functions.

[How]
There are built in functions for extracting global sync params
during mode validation now.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c4e0dbcb

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+5 −44
Original line number Diff line number Diff line
@@ -3069,8 +3069,7 @@ void dcn20_calculate_dlg_params( 
		int pipe_cnt,

		int vlevel)

{

	int i, j, pipe_idx, pipe_idx_unsplit;

	bool visited[MAX_PIPES] = { 0 };

	int i, pipe_idx;



	/* Writeback MCIF_WB arbitration parameters */

	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -3089,55 +3088,17 @@ void dcn20_calculate_dlg_params( 
	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)

		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;



	/*

	 * An artifact of dml pipe split/odm is that pipes get merged back together for

	 * calculation. Therefore we need to only extract for first pipe in ascending index order

	 * and copy into the other split half.

	 */

	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;



		if (!visited[pipe_idx]) {

			display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;

			display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;



			dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];

			dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];

			dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];

			dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];

			/*

			 * j iterates inside pipes array, unlike i which iterates inside

			 * pipe_ctx array

			 */

			if (src->is_hsplit)

				for (j = pipe_idx + 1; j < pipe_cnt; j++) {

					display_pipe_source_params_st *src_j = &pipes[j].pipe.src;

					display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;



					if (src_j->is_hsplit && !visited[j]

							&& src->hsplit_grp == src_j->hsplit_grp) {

						dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];

						dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];

						dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];

						dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];

						visited[j] = true;

					}

				}

			visited[pipe_idx] = true;

			pipe_idx_unsplit++;

		}

		pipe_idx++;

	}



	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);

		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)

			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

		ASSERT(visited[pipe_idx]);

		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

		pipe_idx++;

	}

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c

+1 −13
Original line number Diff line number Diff line
@@ -154,23 +154,11 @@ dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_c_in_us, mode_lib->vba.TimeP 
dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_l_in_us, mode_lib->vba.TimePerMetaChunkFlip);

dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_c_in_us, mode_lib->vba.TimePerChromaMetaChunkFlip);



dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup);

dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix);

dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);

dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);



unsigned int get_vstartup_calculated(

		struct display_mode_lib *mode_lib,

		const display_e2e_pipe_params_st *pipes,

		unsigned int num_pipes,

		unsigned int which_pipe)

{

	unsigned int which_plane;



	recalculate_params(mode_lib, pipes, num_pipes);

	which_plane = mode_lib->vba.pipe_plane[which_pipe];

	return mode_lib->vba.VStartup[which_plane];

}



double get_total_immediate_flip_bytes(

		struct display_mode_lib *mode_lib,

		const display_e2e_pipe_params_st *pipes,

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h

+1 −6
Original line number Diff line number Diff line
@@ -98,16 +98,11 @@ dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us); 
dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);

dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);



dml_get_pipe_attr_decl(vstartup);

dml_get_pipe_attr_decl(vupdate_offset);

dml_get_pipe_attr_decl(vupdate_width);

dml_get_pipe_attr_decl(vready_offset);



unsigned int get_vstartup_calculated(

		struct display_mode_lib *mode_lib,

		const display_e2e_pipe_params_st *pipes,

		unsigned int num_pipes,

		unsigned int which_pipe);



double get_total_immediate_flip_bytes(

		struct display_mode_lib *mode_lib,

		const display_e2e_pipe_params_st *pipes,