Commit 5debcd01 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-silabs' into clk-next 

 - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
 - Add support for X1830 and X1000 Ingenic SoC clk controllers
 - Add support for Qualcomm's MSM8939 Generic Clock Controller
 - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
 - Enable supply regulators for GPU gdscs on Qualcomm SoCs
 - Add support for Si5342, Si5344 and Si5345 chips

* clk-mmp:
  clk: mmp2: Add audio clock controller driver
  dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
  clk: mmp2: Add support for power islands
  dt-bindings: marvell,mmp2: Add ids for the power domains
  dt-bindings: clock: Make marvell,mmp2-clock a power controller
  clk: mmp2: Add the audio clock
  clk: mmp2: Add the I2S clocks
  clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()
  clk: mmp2: Move thermal register defines up a bit
  dt-bindings: marvell,mmp2: Add clock id for the Audio clock
  dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
  clk: mmp: frac: Allow setting bits other than the numerator/denominator
  clk: mmp: frac: Do not lose last 4 digits of precision

* clk-intel:
  clk: intel: remove redundant initialization of variable rate64
  clk: intel: Add CGU clock driver for a new SoC
  dt-bindings: clk: intel: Add bindings document & header file for CGU

* clk-ingenic:
  clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
  clk: X1000: Add FIXDIV for SSI clock of X1000.
  dt-bindings: clock: Add and reorder ABI for X1000.
  clk: Ingenic: Add CGU driver for X1830.
  dt-bindings: clock: Add X1830 clock bindings.
  clk: Ingenic: Adjust cgu code to make it compatible with X1830.
  clk: Ingenic: Remove unnecessary spinlock when reading registers.

* clk-qcom:
  clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
  dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
  clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
  clk: qcom: gcc: Add support for Secure control source clock
  dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
  clk: qcom: gcc: Add support for a new frequency for SC7180
  clk: qcom: Add DT bindings for MSM8939 GCC
  clk: qcom: gcc: Add missing UFS clocks for SM8150
  clk: qcom: gcc: Add GPU and NPU clocks for SM8150
  clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc
  clk: qcom: gdsc: Handle GDSC regulator supplies
  clk: qcom: msm8916: Fix the address location of pll->config_reg

* clk-silabs:
  clk: clk-si5341: Add support for the Si5345 series
parents b6f3162d 725262d2 d0364663 e480fe10 b1e8d713 f9eec2ea

Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding



maintainers:

  - Rahul Tanwar <rahul.tanwar@linux.intel.com>



description: |

  Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides

  all means to access the CGU hardware module in order to generate a series

  of clocks for the whole system and individual peripherals.



  Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it

  defines all available clocks as macros. These macros can be used in device

  tree sources.



properties:

  compatible:

    const: intel,cgu-lgm



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



examples:

  - |

    cgu: clock-controller@e0200000 {

        compatible = "intel,cgu-lgm";

        reg = <0xe0200000 0x33c>;

        #clock-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/marvell,mmp2-audio-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell MMP2 Audio Clock Controller



maintainers:

  - Lubomir Rintel <lkundrak@v3.sk>



description: |

  The audio clock controller generates and supplies the clocks to the audio

  codec.



  Each clock is assigned an identifier and client nodes use this identifier

  to specify the clock which they consume.



  All these identifiers could be found in

  <dt-bindings/clock/marvell,mmp2-audio.h>.



properties:

  compatible:

    enum:

      - marvell,mmp2-audio-clock



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Audio subsystem clock

      - description: The crystal oscillator clock

      - description: First I2S clock

      - description: Second I2S clock



  clock-names:

    items:

      - const: audio

      - const: vctcxo

      - const: i2s0

      - const: i2s1



  '#clock-cells':

    const: 1



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/marvell,mmp2-audio.h>

    #include <dt-bindings/power/marvell,mmp2.h>



    clock-controller@d42a0c30 {

      compatible = "marvell,mmp2-audio-clock";

      reg = <0xd42a0c30 0x10>;

      clock-names = "audio", "vctcxo", "i2s0", "i2s1";

      clocks = <&soc_clocks MMP2_CLK_AUDIO>,

               <&soc_clocks MMP2_CLK_VCTCXO>,

               <&soc_clocks MMP2_CLK_I2S0>,

               <&soc_clocks MMP2_CLK_I2S1>;

      power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml

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@@ -42,12 +42,16 @@ properties: 
  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



required:

  - compatible

  - reg

  - reg-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false
@@ -61,4 +65,5 @@ examples: 
      reg-names = "mpmu", "apmu", "apbc";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

Documentation/devicetree/bindings/clock/qcom,a53pll.txt

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Qualcomm MSM8916 A53 PLL Binding

--------------------------------

The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies

above 1GHz.



Required properties :

- compatible : Shall contain only one of the following:



		"qcom,msm8916-a53pll"



- reg : shall contain base register location and length



- #clock-cells : must be set to <0>



Example:



	a53pll: clock@b016000 {

		compatible = "qcom,msm8916-a53pll";

		reg = <0xb016000 0x40>;

		#clock-cells = <0>;

	};

Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm A53 PLL Binding



maintainers:

  - Sivaprakash Murugesan <sivaprak@codeaurora.org>



description:

  The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for

  frequencies above 1GHz.



properties:

  compatible:

    const: qcom,msm8916-a53pll



  reg:

    maxItems: 1



  '#clock-cells':

    const: 0



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  #Example 1 - A53 PLL found on MSM8916 devices

  - |

    a53pll: clock@b016000 {

        compatible = "qcom,msm8916-a53pll";

        reg = <0xb016000 0x40>;

        #clock-cells = <0>;

    };