Commit b6f3162d authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2600' into clk-next 

* clk-unisoc:
  clk: sprd: add mipi_csi_xx gate clocks
  clk: sprd: add dt-bindings include for mipi_csi_xx clocks
  dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A
  clk: sprd: check its parent status before reading gate clock
  clk: sprd: return correct type of value for _sprd_pll_recalc_rate
  clk: sprd: mark the local clock symbols static

* clk-trivial:
  clk: versatile: remove redundant assignment to pointer clk
  clk: clk-xgene: Fix a typo in Kconfig
  clk: Remove unused inline function clk_debug_reparent

* clk-bcm:
  clk: bcm2835: Constify struct debugfs_reg32
  clk: bcm2835: Remove casting to bcm2835_clk_register
  clk: bcm2835: Fix return type of bcm2835_register_gate

* clk-st:
  clk: clk-flexgen: fix clock-critical handling

* clk-ast2600:
  clk: ast2600: Fix AHB clock divider for A1
parents 8c88e568 2c1c9696 6f4d3c13 dc543267 a403bbab 2d491066

Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties: 
      - sprd,sc9863a-rpll

      - sprd,sc9863a-dpll

      - sprd,sc9863a-mm-gate

      - sprd,sc9863a-mm-clk

      - sprd,sc9863a-apapb-gate



  clocks:

drivers/clk/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -267,7 +267,7 @@ config COMMON_CLK_XGENE 
	default ARCH_XGENE

	depends on ARM64 || COMPILE_TEST

	---help---

	  Sypport for the APM X-Gene SoC reference, PLL, and device clocks.

	  Support for the APM X-Gene SoC reference, PLL, and device clocks.



config COMMON_CLK_LOCHNAGAR

	tristate "Cirrus Logic Lochnagar clock driver"

drivers/clk/bcm/clk-bcm2835.c

+43 −37
Original line number Diff line number Diff line
@@ -396,8 +396,8 @@ static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman, 
}



static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,

				  struct debugfs_reg32 *regs, size_t nregs,

				  struct dentry *dentry)

				   const struct debugfs_reg32 *regs,

				   size_t nregs, struct dentry *dentry)

{

	struct debugfs_regset32 *regset;
@@ -1240,7 +1240,7 @@ static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 
	return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;

}



static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {

static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {

	{

		.name = "ctl",

		.offset = 0,
@@ -1296,8 +1296,9 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 
};



static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,

					   const struct bcm2835_pll_data *data)

					   const void *data)

{

	const struct bcm2835_pll_data *pll_data = data;

	struct bcm2835_pll *pll;

	struct clk_init_data init;

	int ret;
@@ -1307,7 +1308,7 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 
	/* All of the PLLs derive from the external oscillator. */

	init.parent_names = &cprman->real_parent_names[0];

	init.num_parents = 1;

	init.name = data->name;

	init.name = pll_data->name;

	init.ops = &bcm2835_pll_clk_ops;

	init.flags = CLK_IGNORE_UNUSED;
@@ -1316,7 +1317,7 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 
		return NULL;



	pll->cprman = cprman;

	pll->data = data;

	pll->data = pll_data;

	pll->hw.init = &init;



	ret = devm_clk_hw_register(cprman->dev, &pll->hw);
@@ -1327,35 +1328,36 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 


static struct clk_hw *

bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,

			     const struct bcm2835_pll_divider_data *data)

			     const void *data)

{

	const struct bcm2835_pll_divider_data *divider_data = data;

	struct bcm2835_pll_divider *divider;

	struct clk_init_data init;

	const char *divider_name;

	int ret;



	if (data->fixed_divider != 1) {

	if (divider_data->fixed_divider != 1) {

		divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,

					      "%s_prediv", data->name);

					      "%s_prediv", divider_data->name);

		if (!divider_name)

			return NULL;

	} else {

		divider_name = data->name;

		divider_name = divider_data->name;

	}



	memset(&init, 0, sizeof(init));



	init.parent_names = &data->source_pll;

	init.parent_names = &divider_data->source_pll;

	init.num_parents = 1;

	init.name = divider_name;

	init.ops = &bcm2835_pll_divider_clk_ops;

	init.flags = data->flags | CLK_IGNORE_UNUSED;

	init.flags = divider_data->flags | CLK_IGNORE_UNUSED;



	divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);

	if (!divider)

		return NULL;



	divider->div.reg = cprman->regs + data->a2w_reg;

	divider->div.reg = cprman->regs + divider_data->a2w_reg;

	divider->div.shift = A2W_PLL_DIV_SHIFT;

	divider->div.width = A2W_PLL_DIV_BITS;

	divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
@@ -1364,7 +1366,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 
	divider->div.table = NULL;



	divider->cprman = cprman;

	divider->data = data;

	divider->data = divider_data;



	ret = devm_clk_hw_register(cprman->dev, &divider->div.hw);

	if (ret)
@@ -1374,20 +1376,22 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 
	 * PLLH's channels have a fixed divide by 10 afterwards, which

	 * is what our consumers are actually using.

	 */

	if (data->fixed_divider != 1) {

		return clk_hw_register_fixed_factor(cprman->dev, data->name,

	if (divider_data->fixed_divider != 1) {

		return clk_hw_register_fixed_factor(cprman->dev,

						    divider_data->name,

						    divider_name,

						    CLK_SET_RATE_PARENT,

						    1,

						    data->fixed_divider);

						    divider_data->fixed_divider);

	}



	return &divider->div.hw;

}



static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,

					  const struct bcm2835_clock_data *data)

					     const void *data)

{

	const struct bcm2835_clock_data *clock_data = data;

	struct bcm2835_clock *clock;

	struct clk_init_data init;

	const char *parents[1 << CM_SRC_BITS];
@@ -1398,8 +1402,8 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 
	 * Replace our strings referencing parent clocks with the

	 * actual clock-output-name of the parent.

	 */

	for (i = 0; i < data->num_mux_parents; i++) {

		parents[i] = data->parents[i];

	for (i = 0; i < clock_data->num_mux_parents; i++) {

		parents[i] = clock_data->parents[i];



		ret = match_string(cprman_parent_names,

				   ARRAY_SIZE(cprman_parent_names),
@@ -1410,18 +1414,18 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 


	memset(&init, 0, sizeof(init));

	init.parent_names = parents;

	init.num_parents = data->num_mux_parents;

	init.name = data->name;

	init.flags = data->flags | CLK_IGNORE_UNUSED;

	init.num_parents = clock_data->num_mux_parents;

	init.name = clock_data->name;

	init.flags = clock_data->flags | CLK_IGNORE_UNUSED;



	/*

	 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate

	 * rate changes on at least of the parents.

	 */

	if (data->set_rate_parent)

	if (clock_data->set_rate_parent)

		init.flags |= CLK_SET_RATE_PARENT;



	if (data->is_vpu_clock) {

	if (clock_data->is_vpu_clock) {

		init.ops = &bcm2835_vpu_clock_clk_ops;

	} else {

		init.ops = &bcm2835_clock_clk_ops;
@@ -1430,7 +1434,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 
		/* If the clock wasn't actually enabled at boot, it's not

		 * critical.

		 */

		if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))

		if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))

			init.flags &= ~CLK_IS_CRITICAL;

	}
@@ -1439,7 +1443,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 
		return NULL;



	clock->cprman = cprman;

	clock->data = data;

	clock->data = clock_data;

	clock->hw.init = &init;



	ret = devm_clk_hw_register(cprman->dev, &clock->hw);
@@ -1448,25 +1452,27 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 
	return &clock->hw;

}



static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,

					 const struct bcm2835_gate_data *data)

static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,

					    const void *data)

{

	return clk_register_gate(cprman->dev, data->name, data->parent,

	const struct bcm2835_gate_data *gate_data = data;



	return clk_hw_register_gate(cprman->dev, gate_data->name,

				    gate_data->parent,

				    CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,

				 cprman->regs + data->ctl_reg,

				    cprman->regs + gate_data->ctl_reg,

				    CM_GATE_BIT, 0, &cprman->regs_lock);

}



typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,

					       const void *data);

struct bcm2835_clk_desc {

	bcm2835_clk_register clk_register;

	struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,

				       const void *data);

	unsigned int supported;

	const void *data;

};



/* assignment helper macros for different clock types */

#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \

#define _REGISTER(f, s, ...) { .clk_register = f, \

			       .supported = s,				\

			       .data = __VA_ARGS__ }

#define REGISTER_PLL(s, ...)	_REGISTER(&bcm2835_register_pll,	\

drivers/clk/clk-ast2600.c

+25 −6
Original line number Diff line number Diff line
@@ -642,14 +642,22 @@ static const u32 ast2600_a0_axi_ahb_div_table[] = { 
	2, 2, 3, 5,

};



static const u32 ast2600_a1_axi_ahb_div_table[] = {

	4, 6, 2, 4,

static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {

	3, 2, 3, 4,

};



static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {

	3, 4, 6, 8,

};



static const u32 ast2600_a1_axi_ahb200_tbl[] = {

	3, 4, 3, 4, 2, 2, 2, 2,

};



static void __init aspeed_g6_cc(struct regmap *map)

{

	struct clk_hw *hw;

	u32 val, div, chip_id, axi_div, ahb_div;

	u32 val, div, divbits, chip_id, axi_div, ahb_div;



	clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
@@ -679,11 +687,22 @@ static void __init aspeed_g6_cc(struct regmap *map) 
	else

		axi_div = 2;



	divbits = (val >> 11) & 0x3;

	regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);

	if (chip_id & BIT(16))

		ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];

	if (chip_id & BIT(16)) {

		if (!divbits) {

			ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];

			if (val & BIT(16))

				ahb_div *= 2;

		} else {

			if (val & BIT(16))

				ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];

			else

				ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];

		}

	} else {

		ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];

	}



	hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);

	aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;

drivers/clk/clk.c

+0 −4
Original line number Diff line number Diff line
@@ -3295,10 +3295,6 @@ static int __init clk_debug_init(void) 
late_initcall(clk_debug_init);

#else

static inline void clk_debug_register(struct clk_core *core) { }

static inline void clk_debug_reparent(struct clk_core *core,

				      struct clk_core *new_parent)

{

}

static inline void clk_debug_unregister(struct clk_core *core)

{

}